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SWP and SWPB use the same behavior as STR on the ARM9

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This commit is contained in:
Jaklyy 2024-06-25 11:20:01 -04:00
parent 541e1e6388
commit c5b035a973
2 changed files with 9 additions and 6 deletions
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3
src/ARM.h
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@ -144,6 +144,7 @@ public:
virtual void AddCycles_CI(s32 numI) = 0; virtual void AddCycles_CI(s32 numI) = 0;
virtual void AddCycles_CDI_LDR() = 0; virtual void AddCycles_CDI_LDR() = 0;
virtual void AddCycles_CDI_LDM() = 0; virtual void AddCycles_CDI_LDM() = 0;
virtual void AddCycles_CDI_SWP() = 0;
virtual void AddCycles_CD_STR() = 0; virtual void AddCycles_CD_STR() = 0;
virtual void AddCycles_CD_STM() = 0; virtual void AddCycles_CD_STM() = 0;
@ -329,6 +330,7 @@ public:
void AddCycles_CDI_LDR() override; void AddCycles_CDI_LDR() override;
void AddCycles_CDI_LDM() override; void AddCycles_CDI_LDM() override;
void AddCycles_CDI_SWP() override { AddCycles_CD_STR(); } // uses the same behavior as str
void AddCycles_CD_STR() override; void AddCycles_CD_STR() override;
void AddCycles_CD_STM() override; void AddCycles_CD_STM() override;
@ -466,6 +468,7 @@ public:
void AddCycles_CDI(); void AddCycles_CDI();
void AddCycles_CDI_LDR() override { AddCycles_CDI(); } void AddCycles_CDI_LDR() override { AddCycles_CDI(); }
void AddCycles_CDI_LDM() override { AddCycles_CDI(); } void AddCycles_CDI_LDM() override { AddCycles_CDI(); }
void AddCycles_CDI_SWP() override { AddCycles_CDI(); } // checkme?
void AddCycles_CD(); void AddCycles_CD();
void AddCycles_CD_STR() override { AddCycles_CD(); } void AddCycles_CD_STR() override { AddCycles_CD(); }
void AddCycles_CD_STM() override { AddCycles_CD(); } void AddCycles_CD_STM() override { AddCycles_CD(); }

12
src/ARMInterpreter_LoadStore.cpp
View File

@ -462,7 +462,7 @@ void A_SWP(ARM* cpu)
u32 numD = cpu->DataCycles; u32 numD = cpu->DataCycles;
if (cpu->DataWrite32(base, rm)) if (cpu->DataWrite32(base, rm))
{ {
cpu->AddCycles_CDI_LDR(); cpu->AddCycles_CDI_SWP();
// rd only gets updated if both read and write succeed // rd only gets updated if both read and write succeed
u32 rd = (cpu->CurInstr >> 12) & 0xF; u32 rd = (cpu->CurInstr >> 12) & 0xF;
if (rd != 15) if (rd != 15)
@ -484,10 +484,10 @@ void A_SWP(ARM* cpu)
else if (cpu->Num == 1) // for some reason these jumps don't work on the arm 9? else if (cpu->Num == 1) // for some reason these jumps don't work on the arm 9?
cpu->JumpTo(ROR(val, 8*(base&0x3)) & ~1, cpu->ILT_Norm); cpu->JumpTo(ROR(val, 8*(base&0x3)) & ~1, cpu->ILT_Norm);
} }
else cpu->AddCycles_CDI_LDR(); else cpu->AddCycles_CDI_SWP();
cpu->DataCycles += numD; cpu->DataCycles += numD;
} }
else cpu->AddCycles_CDI_LDR(); else cpu->AddCycles_CDI_SWP();
} }
void A_SWPB(ARM* cpu) void A_SWPB(ARM* cpu)
@ -502,7 +502,7 @@ void A_SWPB(ARM* cpu)
u32 numD = cpu->DataCycles; u32 numD = cpu->DataCycles;
if (cpu->DataWrite8(base, rm)) if (cpu->DataWrite8(base, rm))
{ {
cpu->AddCycles_CDI_LDR(); cpu->AddCycles_CDI_SWP();
// rd only gets updated if both read and write succeed // rd only gets updated if both read and write succeed
u32 rd = (cpu->CurInstr >> 12) & 0xF; u32 rd = (cpu->CurInstr >> 12) & 0xF;
if (rd != 15) if (rd != 15)
@ -516,10 +516,10 @@ void A_SWPB(ARM* cpu)
else if (cpu->Num == 1)// for some reason these jumps don't work on the arm 9? else if (cpu->Num == 1)// for some reason these jumps don't work on the arm 9?
cpu->JumpTo(val & ~1); cpu->JumpTo(val & ~1);
} }
else cpu->AddCycles_CDI_LDR(); else cpu->AddCycles_CDI_SWP();
cpu->DataCycles += numD; cpu->DataCycles += numD;
} }
else cpu->AddCycles_CDI_LDR(); else cpu->AddCycles_CDI_SWP();
} }