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JIT: base

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all instructions are interpreted
This commit is contained in:
RSDuck
2019-06-22 01:28:32 +02:00
parent d2f05cd30f
commit c5c342c009
28 changed files with 7743 additions and 4 deletions
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7
src/CP15.cpp
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@ -20,6 +20,7 @@
#include <string.h>
#include "NDS.h"
#include "ARM.h"
#include "ARMJIT.h"
// access timing for cached regions
@ -811,6 +812,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
{
DataCycles = 1;
*(u8*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -832,6 +834,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
{
DataCycles = 1;
*(u16*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -853,6 +856,8 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
{
DataCycles = 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::cache.ARM9_ITCM[((addr + 2) & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -874,6 +879,8 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
{
DataCycles += 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2] = NULL;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2 + 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))