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JIT: base

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all instructions are interpreted
This commit is contained in:
RSDuck
2019-06-22 01:28:32 +02:00
parent aa6ff499f9
commit c692287eba
27 changed files with 7700 additions and 2 deletions
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7
src/CP15.cpp
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@ -21,6 +21,7 @@
#include "NDS.h"
#include "DSi.h"
#include "ARM.h"
#include "ARMJIT.h"
// access timing for cached regions
@ -812,6 +813,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
{
DataCycles = 1;
*(u8*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -833,6 +835,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
{
DataCycles = 1;
*(u16*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -854,6 +857,8 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
{
DataCycles = 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
ARMJIT::cache.ARM9_ITCM[((addr + 2) & 0x7FFF) >> 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
@ -875,6 +880,8 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
{
DataCycles += 1;
*(u32*)&ITCM[addr & 0x7FFF] = val;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2] = NULL;
ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2 + 1] = NULL;
return;
}
if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))