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https://github.com/melonDS-emu/melonDS.git
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JIT: base
all instructions are interpreted
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@ -21,6 +21,7 @@
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#include "NDS.h"
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#include "DSi.h"
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#include "ARM.h"
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#include "ARMJIT.h"
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// access timing for cached regions
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@ -812,6 +813,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
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{
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DataCycles = 1;
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*(u8*)&ITCM[addr & 0x7FFF] = val;
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ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
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return;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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@ -833,6 +835,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
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{
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DataCycles = 1;
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*(u16*)&ITCM[addr & 0x7FFF] = val;
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ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
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return;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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@ -854,6 +857,8 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
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{
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DataCycles = 1;
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*(u32*)&ITCM[addr & 0x7FFF] = val;
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ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) >> 1] = NULL;
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ARMJIT::cache.ARM9_ITCM[((addr + 2) & 0x7FFF) >> 1] = NULL;
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return;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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@ -875,6 +880,8 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
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{
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DataCycles += 1;
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*(u32*)&ITCM[addr & 0x7FFF] = val;
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ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2] = NULL;
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ARMJIT::cache.ARM9_ITCM[(addr & 0x7FFF) / 2 + 1] = NULL;
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return;
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}
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if (addr >= DTCMBase && addr < (DTCMBase + DTCMSize))
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