mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
DMA timing renovation (#1207)
* make timers usable for measurement shito without being assfuckingly unreliable * bürp * Arisotura can you ever clean up your goddamn code also regroup the timer code instead of having it split weirdly * make the set-timing functions a tad less hacky * congrats Arisotura you made an ass-enum * add timing region tables, and separate timings for ARM9 DMA (exempt of 3c penalty) * temp work on DMA timings, not finished also, did you know? 'increment/reload' is also a thing for the source address * begin work * add some of the GBA slot/wifi timings * complete it, I guess * make some progress * getting somewhere * sdsdfs * see, Arisotura, was it that hard? blarg.
This commit is contained in:
468
src/DMA.cpp
468
src/DMA.cpp
@ -21,6 +21,7 @@
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#include "DSi.h"
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#include "DMA.h"
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#include "GPU.h"
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#include "DMA_Timings.h"
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@ -77,6 +78,7 @@ void DMA::Reset()
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Running = false;
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InProgress = false;
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MRAMBurstCount = 0;
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}
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void DMA::DoSavestate(Savestate* file)
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@ -94,12 +96,13 @@ void DMA::DoSavestate(Savestate* file)
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file->Var32(&CurDstAddr);
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file->Var32(&RemCount);
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file->Var32(&IterCount);
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file->Var32(&SrcAddrInc);
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file->Var32(&DstAddrInc);
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file->Var32((u32*)&SrcAddrInc);
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file->Var32((u32*)&DstAddrInc);
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file->Var32(&Running);
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file->Bool32(&InProgress);
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file->Bool32(&IsGXFIFODMA);
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file->Var32(&MRAMBurstCount);
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}
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void DMA::WriteCnt(u32 val)
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@ -125,7 +128,7 @@ void DMA::WriteCnt(u32 val)
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case 0x00000000: SrcAddrInc = 1; break;
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case 0x00800000: SrcAddrInc = -1; break;
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case 0x01000000: SrcAddrInc = 0; break;
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case 0x01800000: SrcAddrInc = 1; printf("BAD DMA SRC INC MODE 3\n"); break;
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case 0x01800000: SrcAddrInc = 1; break;
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}
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if (CPU == 0)
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@ -165,6 +168,9 @@ void DMA::Start()
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else
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IterCount = RemCount;
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if ((Cnt & 0x01800000) == 0x01800000)
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CurSrcAddr = SrcAddr;
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if ((Cnt & 0x00600000) == 0x00600000)
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CurDstAddr = DstAddr;
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@ -174,15 +180,369 @@ void DMA::Start()
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// TODO eventually: not stop if we're running code in ITCM
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if (NDS::DMAsRunning(CPU))
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Running = 1;
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else
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Running = 2;
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Running = 2;
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// safety measure
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MRAMBurstTable = DMATiming::MRAMDummy;
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InProgress = true;
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NDS::StopCPU(CPU, 1<<Num);
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}
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u32 DMA::UnitTimings9_16(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 14;
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u32 dst_id = CurDstAddr >> 14;
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u32 src_rgn = NDS::ARM9Regions[src_id];
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u32 dst_rgn = NDS::ARM9Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM9MemTimings[src_id][4];
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src_s = NDS::ARM9MemTimings[src_id][5];
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dst_n = NDS::ARM9MemTimings[dst_id][4];
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dst_s = NDS::ARM9MemTimings[dst_id][5];
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if (src_rgn == NDS::Mem9_MainRAM)
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{
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if (dst_rgn == NDS::Mem9_MainRAM)
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return 16;
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if (SrcAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (dst_rgn == NDS::Mem9_GBAROM)
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{
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if (dst_s == 4)
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[0];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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// TODO: not quite right for GBA slot
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return (((CurSrcAddr & 0x1F) == 0x1E) ? 7 : 8) +
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(burststart ? dst_n : dst_s);
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}
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}
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else if (dst_rgn == NDS::Mem9_MainRAM)
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{
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if (DstAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (src_rgn == NDS::Mem9_GBAROM)
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{
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if (src_s == 4)
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[0];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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return (burststart ? src_n : src_s) + 7;
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}
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}
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else if (src_rgn & dst_rgn)
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{
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return src_n + dst_n + 1;
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}
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else
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{
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if (burststart)
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return src_n + dst_n;
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else
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return src_s + dst_s;
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}
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}
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u32 DMA::UnitTimings9_32(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 14;
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u32 dst_id = CurDstAddr >> 14;
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u32 src_rgn = NDS::ARM9Regions[src_id];
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u32 dst_rgn = NDS::ARM9Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM9MemTimings[src_id][6];
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src_s = NDS::ARM9MemTimings[src_id][7];
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dst_n = NDS::ARM9MemTimings[dst_id][6];
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dst_s = NDS::ARM9MemTimings[dst_id][7];
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if (src_rgn == NDS::Mem9_MainRAM)
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{
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if (dst_rgn == NDS::Mem9_MainRAM)
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return 18;
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if (SrcAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (dst_rgn == NDS::Mem9_GBAROM)
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{
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if (dst_s == 8)
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[2];
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else
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[3];
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}
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else if (dst_n == 2)
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[0];
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else
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[1];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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// TODO: not quite right for GBA slot
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return (((CurSrcAddr & 0x1F) == 0x1C) ? (dst_n==2 ? 7:8) : 9) +
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(burststart ? dst_n : dst_s);
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}
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}
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else if (dst_rgn == NDS::Mem9_MainRAM)
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{
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if (DstAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (src_rgn == NDS::Mem9_GBAROM)
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{
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if (src_s == 8)
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[2];
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else
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[3];
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}
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else if (src_n == 2)
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[0];
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else
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[1];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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return (burststart ? src_n : src_s) + 8;
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}
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}
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else if (src_rgn & dst_rgn)
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{
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return src_n + dst_n + 1;
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}
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else
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{
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if (burststart)
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return src_n + dst_n;
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else
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return src_s + dst_s;
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}
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}
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// TODO: the ARM7 ones don't take into account that the two wifi regions have different timings
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u32 DMA::UnitTimings7_16(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 15;
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u32 dst_id = CurDstAddr >> 15;
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u32 src_rgn = NDS::ARM7Regions[src_id];
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u32 dst_rgn = NDS::ARM7Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM7MemTimings[src_id][0];
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src_s = NDS::ARM7MemTimings[src_id][1];
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dst_n = NDS::ARM7MemTimings[dst_id][0];
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dst_s = NDS::ARM7MemTimings[dst_id][1];
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if (src_rgn == NDS::Mem7_MainRAM)
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{
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if (dst_rgn == NDS::Mem7_MainRAM)
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return 16;
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if (SrcAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (dst_rgn == NDS::Mem7_GBAROM || dst_rgn == NDS::Mem7_Wifi0 || dst_rgn == NDS::Mem7_Wifi1)
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{
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if (dst_s == 4)
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMRead16Bursts[0];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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// TODO: not quite right for GBA slot
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return (((CurSrcAddr & 0x1F) == 0x1E) ? 7 : 8) +
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(burststart ? dst_n : dst_s);
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}
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}
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else if (dst_rgn == NDS::Mem7_MainRAM)
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{
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if (DstAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (src_rgn == NDS::Mem7_GBAROM || src_rgn == NDS::Mem7_Wifi0 || src_rgn == NDS::Mem7_Wifi1)
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{
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if (src_s == 4)
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[1];
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[2];
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}
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else
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MRAMBurstTable = DMATiming::MRAMWrite16Bursts[0];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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return (burststart ? src_n : src_s) + 7;
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}
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}
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else if (src_rgn & dst_rgn)
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{
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return src_n + dst_n + 1;
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}
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else
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{
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if (burststart)
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return src_n + dst_n;
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else
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return src_s + dst_s;
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}
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}
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u32 DMA::UnitTimings7_32(bool burststart)
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{
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u32 src_id = CurSrcAddr >> 15;
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u32 dst_id = CurDstAddr >> 15;
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u32 src_rgn = NDS::ARM7Regions[src_id];
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u32 dst_rgn = NDS::ARM7Regions[dst_id];
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u32 src_n, src_s, dst_n, dst_s;
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src_n = NDS::ARM7MemTimings[src_id][2];
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src_s = NDS::ARM7MemTimings[src_id][3];
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dst_n = NDS::ARM7MemTimings[dst_id][2];
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dst_s = NDS::ARM7MemTimings[dst_id][3];
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if (src_rgn == NDS::Mem7_MainRAM)
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{
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if (dst_rgn == NDS::Mem7_MainRAM)
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return 18;
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if (SrcAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (dst_rgn == NDS::Mem7_GBAROM || dst_rgn == NDS::Mem7_Wifi0 || dst_rgn == NDS::Mem7_Wifi1)
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{
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if (dst_s == 8)
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[2];
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else
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[3];
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}
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else if (dst_n == 2)
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[0];
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else
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MRAMBurstTable = DMATiming::MRAMRead32Bursts[1];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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// TODO: not quite right for GBA slot
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return (((CurSrcAddr & 0x1F) == 0x1C) ? (dst_n==2 ? 7:8) : 9) +
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(burststart ? dst_n : dst_s);
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}
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}
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else if (dst_rgn == NDS::Mem7_MainRAM)
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{
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if (DstAddrInc > 0)
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{
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if (burststart || MRAMBurstTable[MRAMBurstCount] == 0)
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{
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MRAMBurstCount = 0;
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if (src_rgn == NDS::Mem7_GBAROM || src_rgn == NDS::Mem7_Wifi0 || src_rgn == NDS::Mem7_Wifi1)
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{
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if (src_s == 8)
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[2];
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else
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[3];
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}
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else if (src_n == 2)
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[0];
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else
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MRAMBurstTable = DMATiming::MRAMWrite32Bursts[1];
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}
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u32 ret = MRAMBurstTable[MRAMBurstCount++];
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return ret;
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}
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else
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{
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return (burststart ? src_n : src_s) + 8;
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}
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}
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else if (src_rgn & dst_rgn)
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{
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return src_n + dst_n + 1;
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}
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else
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{
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if (burststart)
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return src_n + dst_n;
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else
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return src_s + dst_s;
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}
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}
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template <int ConsoleType>
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void DMA::Run9()
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{
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@ -194,32 +554,12 @@ void DMA::Run9()
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bool burststart = (Running == 2);
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Running = 1;
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s32 unitcycles;
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//s32 lastcycles = cycles;
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if (!(Cnt & (1<<26)))
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{
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0];
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}
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else
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][1] + NDS::ARM9MemTimings[CurDstAddr >> 14][1];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][0] + NDS::ARM9MemTimings[CurDstAddr >> 14][0]);
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cycles += unitcycles;
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}*/
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}
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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NDS::ARM9Timestamp += (UnitTimings9_16(burststart) << NDS::ARM9ClockShift);
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burststart = false;
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|
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if (ConsoleType == 1)
|
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DSi::ARM9Write16(CurDstAddr, DSi::ARM9Read16(CurSrcAddr));
|
||||
@ -236,29 +576,10 @@ void DMA::Run9()
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
|
||||
{
|
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2];
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}
|
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else
|
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{
|
||||
unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3];
|
||||
if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
|
||||
unitcycles++;
|
||||
else if ((CurSrcAddr >> 24) == 0x02)
|
||||
unitcycles--;
|
||||
|
||||
/*if (burststart)
|
||||
{
|
||||
cycles -= 2;
|
||||
cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]);
|
||||
cycles += unitcycles;
|
||||
}*/
|
||||
}
|
||||
|
||||
while (IterCount > 0 && !Stall)
|
||||
{
|
||||
NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
|
||||
NDS::ARM9Timestamp += (UnitTimings9_32(burststart) << NDS::ARM9ClockShift);
|
||||
burststart = false;
|
||||
|
||||
if (ConsoleType == 1)
|
||||
DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr));
|
||||
@ -313,32 +634,12 @@ void DMA::Run7()
|
||||
bool burststart = (Running == 2);
|
||||
Running = 1;
|
||||
|
||||
s32 unitcycles;
|
||||
//s32 lastcycles = cycles;
|
||||
|
||||
if (!(Cnt & (1<<26)))
|
||||
{
|
||||
if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
|
||||
{
|
||||
unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0];
|
||||
}
|
||||
else
|
||||
{
|
||||
unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][1] + NDS::ARM7MemTimings[CurDstAddr >> 15][1];
|
||||
if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
|
||||
unitcycles++;
|
||||
|
||||
/*if (burststart)
|
||||
{
|
||||
cycles -= 2;
|
||||
cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][0] + NDS::ARM7MemTimings[CurDstAddr >> 15][0]);
|
||||
cycles += unitcycles;
|
||||
}*/
|
||||
}
|
||||
|
||||
while (IterCount > 0 && !Stall)
|
||||
{
|
||||
NDS::ARM7Timestamp += unitcycles;
|
||||
NDS::ARM7Timestamp += UnitTimings7_16(burststart);
|
||||
burststart = false;
|
||||
|
||||
if (ConsoleType == 1)
|
||||
DSi::ARM7Write16(CurDstAddr, DSi::ARM7Read16(CurSrcAddr));
|
||||
@ -355,29 +656,10 @@ void DMA::Run7()
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
|
||||
{
|
||||
unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2];
|
||||
}
|
||||
else
|
||||
{
|
||||
unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3];
|
||||
if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
|
||||
unitcycles++;
|
||||
else if ((CurSrcAddr >> 24) == 0x02)
|
||||
unitcycles--;
|
||||
|
||||
/*if (burststart)
|
||||
{
|
||||
cycles -= 2;
|
||||
cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]);
|
||||
cycles += unitcycles;
|
||||
}*/
|
||||
}
|
||||
|
||||
while (IterCount > 0 && !Stall)
|
||||
{
|
||||
NDS::ARM7Timestamp += unitcycles;
|
||||
NDS::ARM7Timestamp += UnitTimings7_32(burststart);
|
||||
burststart = false;
|
||||
|
||||
if (ConsoleType == 1)
|
||||
DSi::ARM7Write32(CurDstAddr, DSi::ARM7Read32(CurSrcAddr));
|
||||
|
Reference in New Issue
Block a user