mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 14:19:55 -06:00
tremble upon the NDMA implementation
that doesn't do much beyond getting stuck
This commit is contained in:
Arisotura
301
src/DSi_NDMA.cpp
301
src/DSi_NDMA.cpp
@ -15,3 +15,304 @@
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include "NDS.h"
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#include "DSi.h"
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#include "DSi_NDMA.h"
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#include "GPU.h"
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DSi_NDMA::DSi_NDMA(u32 cpu, u32 num)
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{
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CPU = cpu;
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Num = num;
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Reset();
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}
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DSi_NDMA::~DSi_NDMA()
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{
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}
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void DSi_NDMA::Reset()
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{
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SrcAddr = 0;
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DstAddr = 0;
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TotalLength = 0;
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BlockLength = 0;
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SubblockTimer = 0;
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FillData = 0;
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Cnt = 0;
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StartMode = 0;
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CurSrcAddr = 0;
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CurDstAddr = 0;
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SubblockLength = 0;
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RemCount = 0;
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IterCount = 0;
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TotalRemCount = 0;
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SrcAddrInc = 0;
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DstAddrInc = 0;
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Running = false;
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InProgress = false;
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}
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void DSi_NDMA::DoSavestate(Savestate* file)
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{
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// TODO!
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}
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void DSi_NDMA::WriteCnt(u32 val)
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{
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u32 oldcnt = Cnt;
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Cnt = val;
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if ((!(oldcnt & 0x80000000)) && (val & 0x80000000)) // checkme
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{
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CurSrcAddr = SrcAddr;
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CurDstAddr = DstAddr;
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TotalRemCount = TotalLength;
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switch ((Cnt >> 10) & 0x3)
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{
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case 0: DstAddrInc = 1; break;
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case 1: DstAddrInc = -1; break;
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case 2: DstAddrInc = 0; break;
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case 3: DstAddrInc = 1; printf("BAD NDMA DST INC MODE 3\n"); break;
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}
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switch ((Cnt >> 13) & 0x3)
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{
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case 0: SrcAddrInc = 1; break;
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case 1: SrcAddrInc = -1; break;
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case 2: SrcAddrInc = 0; break;
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case 3: SrcAddrInc = 0; break; // fill mode
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}
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StartMode = (Cnt >> 24) & 0x1F;
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if (StartMode > 0x10) StartMode = 0x10;
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if (CPU == 1) StartMode |= 0x20;
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if ((StartMode & 0x1F) == 0x10)
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Start();
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if (StartMode != 0x10 && StartMode != 0x30)
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printf("UNIMPLEMENTED ARM%d NDMA%d START MODE %02X, %08X->%08X\n", CPU?7:9, Num, StartMode, SrcAddr, DstAddr);
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}
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}
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void DSi_NDMA::Start()
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{
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if (Running) return;
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if (!InProgress)
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{
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RemCount = BlockLength;
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if (!RemCount)
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RemCount = 0x1000000;
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}
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// TODO: how does GXFIFO DMA work with all the block shito?
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IterCount = RemCount;
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if (IterCount > TotalRemCount)
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IterCount = TotalRemCount;
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if (Cnt & (1<<12)) CurDstAddr = DstAddr;
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if (Cnt & (1<<15)) CurSrcAddr = SrcAddr;
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printf("ARM%d NDMA%d %08X %02X %08X->%08X %d bytes\n", CPU?7:9, Num, Cnt, StartMode, CurSrcAddr, CurDstAddr, RemCount*4);
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//IsGXFIFODMA = (CPU == 0 && (CurSrcAddr>>24) == 0x02 && CurDstAddr == 0x04000400 && DstAddrInc == 0);
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// TODO eventually: not stop if we're running code in ITCM
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if (SubblockTimer & 0xFFFF)
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printf("TODO! NDMA SUBBLOCK TIMER: %08X\n", SubblockTimer);
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if (NDS::DMAsRunning(CPU))
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Running = 1;
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else
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Running = 2;
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InProgress = true;
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NDS::StopCPU(CPU, 1<<(Num+4));
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}
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void DSi_NDMA::Run()
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{
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if (!Running) return;
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if (CPU == 0) return Run9();
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else return Run7();
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}
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void DSi_NDMA::Run9()
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{
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if (NDS::ARM9Timestamp >= NDS::ARM9Target) return;
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Executing = true;
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// add NS penalty for first accesses in burst
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bool burststart = (Running == 2);
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Running = 1;
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s32 unitcycles;
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//s32 lastcycles = cycles;
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bool dofill = ((Cnt >> 13) & 0x3) == 3;
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2];
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}
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else
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{
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unitcycles = NDS::ARM9MemTimings[CurSrcAddr >> 14][3] + NDS::ARM9MemTimings[CurDstAddr >> 14][3];
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if ((CurSrcAddr >> 24) == (CurDstAddr >> 24))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM9MemTimings[CurSrcAddr >> 14][2] + NDS::ARM9MemTimings[CurDstAddr >> 14][2]);
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cycles += unitcycles;
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}*/
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}
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM9Timestamp += (unitcycles << NDS::ARM9ClockShift);
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if (dofill)
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DSi::ARM9Write32(CurDstAddr, FillData);
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else
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DSi::ARM9Write32(CurDstAddr, DSi::ARM9Read32(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<2;
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CurDstAddr += DstAddrInc<<2;
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IterCount--;
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RemCount--;
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TotalRemCount--;
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if (NDS::ARM9Timestamp >= NDS::ARM9Target) break;
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}
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Executing = false;
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Stall = false;
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if (RemCount)
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{
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if (IterCount == 0)
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{
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Running = 0;
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NDS::ResumeCPU(0, 1<<(Num+4));
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//if (StartMode == 0x07)
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// GPU3D::CheckFIFODMA();
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}
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return;
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}
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if ((StartMode & 0x1F) == 0x10) // CHECKME
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Cnt &= ~(1<<31);
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else if (!(Cnt & (1<<29)))
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{
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if (TotalRemCount == 0)
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Cnt &= ~(1<<31);
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}
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if (Cnt & (1<<30))
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NDS::SetIRQ(0, NDS::IRQ_DSi_NDMA0 + Num);
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Running = 0;
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InProgress = false;
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NDS::ResumeCPU(0, 1<<(Num+4));
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}
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void DSi_NDMA::Run7()
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{
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if (NDS::ARM7Timestamp >= NDS::ARM7Target) return;
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Executing = true;
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// add NS penalty for first accesses in burst
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bool burststart = (Running == 2);
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Running = 1;
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s32 unitcycles;
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//s32 lastcycles = cycles;
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bool dofill = ((Cnt >> 13) & 0x3) == 3;
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if ((CurSrcAddr >> 24) == 0x02 && (CurDstAddr >> 24) == 0x02)
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2];
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}
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else
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{
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unitcycles = NDS::ARM7MemTimings[CurSrcAddr >> 15][3] + NDS::ARM7MemTimings[CurDstAddr >> 15][3];
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if ((CurSrcAddr >> 23) == (CurDstAddr >> 23))
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unitcycles++;
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else if ((CurSrcAddr >> 24) == 0x02)
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unitcycles--;
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/*if (burststart)
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{
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cycles -= 2;
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cycles -= (NDS::ARM7MemTimings[CurSrcAddr >> 15][2] + NDS::ARM7MemTimings[CurDstAddr >> 15][2]);
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cycles += unitcycles;
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}*/
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}
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while (IterCount > 0 && !Stall)
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{
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NDS::ARM7Timestamp += unitcycles;
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if (dofill)
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DSi::ARM7Write32(CurDstAddr, FillData);
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else
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DSi::ARM7Write32(CurDstAddr, DSi::ARM7Read32(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<2;
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CurDstAddr += DstAddrInc<<2;
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IterCount--;
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RemCount--;
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if (NDS::ARM7Timestamp >= NDS::ARM7Target) break;
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}
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Executing = false;
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Stall = false;
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if (RemCount)
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{
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if (IterCount == 0)
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{
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Running = 0;
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NDS::ResumeCPU(1, 1<<(Num+4));
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}
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return;
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}
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if ((StartMode & 0x1F) == 0x10) // CHECKME
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Cnt &= ~(1<<31);
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else if (!(Cnt & (1<<29)))
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{
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if (TotalRemCount == 0)
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Cnt &= ~(1<<31);
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}
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if (Cnt & (1<<30))
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NDS::SetIRQ(1, NDS::IRQ_DSi_NDMA0 + Num);
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Running = 0;
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InProgress = false;
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NDS::ResumeCPU(1, 1<<(Num+4));
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}
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