mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-27 00:00:07 -06:00
improve stm timings
need to verify if they apply to all store instructions
This commit is contained in:
42
src/ARM.cpp
42
src/ARM.cpp
@ -1259,6 +1259,31 @@ bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
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}
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void ARMv5::AddCycles_CD()
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{
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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s32 numD = DataCycles;
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s32 early;
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if (DataRegion == Mem9_ITCM)
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{
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early = (CodeRegion == Mem9_ITCM) ? -1 : 0;
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}
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else if (DataRegion == Mem9_DTCM)
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{
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early = 2;
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}
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else if (DataRegion == Mem9_MainRAM)
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{
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early = (CodeRegion == Mem9_MainRAM) ? 0 : 18; // CHECKME: how early can main ram be?
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}
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else early = (DataRegion == CodeRegion) ? 4 : 6;
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s32 code = numC - early;
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if (code < 0) code = 0;
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Cycles += std::max(code + numD, numC);
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}
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void ARMv5::AddCycles_CDI()
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{
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// LDR/LDM cycles. ARM9 seems to skip the internal cycle there.
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@ -1269,7 +1294,7 @@ void ARMv5::AddCycles_CDI()
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s32 early;
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switch (DataRegion)
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{
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case 0: // background region; CHECKME
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case 0: // background region;
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case Mem9_DTCM:
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case Mem9_BIOS:
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case Mem9_WRAM:
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@ -1297,17 +1322,10 @@ void ARMv5::AddCycles_CDI()
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early = (CodeRegion == Mem9_ITCM) ? -1 : 0;
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break;
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}
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if (numD > early)
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{
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numC -= early;
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if (numC < 0) numC = 0;
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Cycles += numC + numD;
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}
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else
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{
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Cycles += numC;
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}
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s32 code = numC - early;
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if (code < 0) code = 0;
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Cycles += std::max(code + numD, numC);
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}
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void ARMv4::AddCycles_C()
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