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improve stm timings

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need to verify if they apply to all store instructions
This commit is contained in:
Jaklyy
2024-06-24 22:50:04 -04:00
parent 109bbed3d0
commit dbe00e72dd
3 changed files with 40 additions and 29 deletions
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15
src/CP15.cpp
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@ -934,10 +934,9 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
return false;
}
DataRegion = addr;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@ -945,12 +944,14 @@ bool ARMv5::DataWrite8(u32 addr, u8 val)
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*(u8*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return true;
}
BusWrite8(addr, val);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][1];
return true;
}
@ -963,12 +964,11 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
return false;
}
DataRegion = addr;
addr &= ~1;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@ -976,12 +976,14 @@ bool ARMv5::DataWrite16(u32 addr, u16 val)
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*(u16*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return true;
}
BusWrite16(addr, val);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][1];
return true;
}
@ -994,12 +996,11 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
return false;
}
DataRegion = addr;
addr &= ~3;
if (addr < ITCMSize)
{
DataRegion = Mem9_ITCM;
DataCycles = 1;
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
@ -1007,12 +1008,14 @@ bool ARMv5::DataWrite32(u32 addr, u32 val)
}
if ((addr & DTCMMask) == DTCMBase)
{
DataRegion = Mem9_DTCM;
DataCycles = 1;
*(u32*)&DTCM[addr & (DTCMPhysicalSize - 1)] = val;
return true;
}
BusWrite32(addr, val);
DataRegion = NDS.ARM9Regions[addr >> 14];
DataCycles = MemTimings[addr >> 12][2];
return true;
}