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fix performance regression for disabling interlock emulation path

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Jaklyy 2024-06-15 18:47:56 -04:00
parent 449557624d
commit debaaa0425
1 changed files with 19 additions and 7 deletions
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22
src/ARM.h
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@ -145,6 +145,7 @@ public:
virtual void AddCycles_CDI() = 0; virtual void AddCycles_CDI() = 0;
virtual void AddCycles_CD() = 0; virtual void AddCycles_CD() = 0;
/*
inline void AddCycles_L(const u32 delay, const u32 reg1) inline void AddCycles_L(const u32 delay, const u32 reg1)
{ {
if (InterlockTimestamp[reg1] > Timestamp() + delay); if (InterlockTimestamp[reg1] > Timestamp() + delay);
@ -163,13 +164,24 @@ public:
u64 cycles = std::max(InterlockTimestamp[reg1], std::max(InterlockTimestamp[reg2], InterlockTimestamp[reg3])); u64 cycles = std::max(InterlockTimestamp[reg1], std::max(InterlockTimestamp[reg2], InterlockTimestamp[reg3]));
if (cycles > Timestamp() + delay) if (cycles > Timestamp() + delay)
Timestamp() = cycles; Timestamp() = cycles;
} }*/
#ifdef INTERLOCK
// fetch the value of a register while handling any interlock cycles // fetch the value of a register while handling any interlock cycles
virtual inline u32 GetReg(const u32 reg, const u32 delay = 0) = 0; virtual inline u32 GetReg(const u32 reg, const u32 delay = 0) = 0;
// Must be called after all of an instruction's cycles are calculated!!! // Must be called after all of an instruction's cycles are calculated!!!
virtual inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) = 0; virtual inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) = 0;
#else
// fetch the value of a register while handling any interlock cycles
inline u32 GetReg(const u32 reg, const u32 delay = 0)
{
return R[reg];
}
// Must be called after all of an instruction's cycles are calculated!!!
inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) {}
#endif
virtual u64& Timestamp() = 0; virtual u64& Timestamp() = 0;
@ -338,24 +350,22 @@ public:
// Cycles += numC + numD; // Cycles += numC + numD;
} }
#ifdef INTERLOCK
// fetch the value of a register while handling any interlock cycles // fetch the value of a register while handling any interlock cycles
inline u32 GetReg(const u32 reg, const u32 delay = 0) override inline u32 GetReg(const u32 reg, const u32 delay = 0) override
{ {
#ifdef INTERLOCK
if (InterlockTimestamp[reg] > (Timestamp() + delay)) if (InterlockTimestamp[reg] > (Timestamp() + delay))
Timestamp() = InterlockTimestamp[reg] - delay; Timestamp() = InterlockTimestamp[reg] - delay;
#endif
return R[reg]; return R[reg];
} }
// Must be called after all of an instruction's cycles are calculated!!! // Must be called after all of an instruction's cycles are calculated!!!
inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override
{ {
#ifdef INTERLOCK
InterlockTimestamp[reg] = cycles + Timestamp() + Cycles; InterlockTimestamp[reg] = cycles + Timestamp() + Cycles;
//InterlockType[reg] = type; //InterlockType[reg] = type;
#endif
} }
#endif
u64& Timestamp() override; u64& Timestamp() override;
@ -474,6 +484,7 @@ public:
void AddCycles_CDI() override; void AddCycles_CDI() override;
void AddCycles_CD() override; void AddCycles_CD() override;
#ifdef INTERLOCK
// fetch the value of a register while handling any interlock cycles // fetch the value of a register while handling any interlock cycles
inline u32 GetReg(const u32 reg, const u32 delay = 0) override inline u32 GetReg(const u32 reg, const u32 delay = 0) override
{ {
@ -482,6 +493,7 @@ public:
// Must be called after all of an instruction's cycles are calculated!!! // Must be called after all of an instruction's cycles are calculated!!!
inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override{} inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override{}
#endif
u64& Timestamp() override; u64& Timestamp() override;
protected: protected: