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https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
fix performance regression for disabling interlock emulation path
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parent
449557624d
commit
debaaa0425
26
src/ARM.h
26
src/ARM.h
@ -145,6 +145,7 @@ public:
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virtual void AddCycles_CDI() = 0;
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virtual void AddCycles_CDI() = 0;
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virtual void AddCycles_CD() = 0;
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virtual void AddCycles_CD() = 0;
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/*
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inline void AddCycles_L(const u32 delay, const u32 reg1)
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inline void AddCycles_L(const u32 delay, const u32 reg1)
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{
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{
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if (InterlockTimestamp[reg1] > Timestamp() + delay);
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if (InterlockTimestamp[reg1] > Timestamp() + delay);
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@ -163,13 +164,24 @@ public:
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u64 cycles = std::max(InterlockTimestamp[reg1], std::max(InterlockTimestamp[reg2], InterlockTimestamp[reg3]));
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u64 cycles = std::max(InterlockTimestamp[reg1], std::max(InterlockTimestamp[reg2], InterlockTimestamp[reg3]));
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if (cycles > Timestamp() + delay)
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if (cycles > Timestamp() + delay)
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Timestamp() = cycles;
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Timestamp() = cycles;
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}
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}*/
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#ifdef INTERLOCK
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// fetch the value of a register while handling any interlock cycles
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// fetch the value of a register while handling any interlock cycles
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virtual inline u32 GetReg(const u32 reg, const u32 delay = 0) = 0;
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virtual inline u32 GetReg(const u32 reg, const u32 delay = 0) = 0;
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// Must be called after all of an instruction's cycles are calculated!!!
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// Must be called after all of an instruction's cycles are calculated!!!
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virtual inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) = 0;
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virtual inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) = 0;
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#else
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// fetch the value of a register while handling any interlock cycles
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inline u32 GetReg(const u32 reg, const u32 delay = 0)
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{
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return R[reg];
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}
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// Must be called after all of an instruction's cycles are calculated!!!
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inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) {}
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#endif
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virtual u64& Timestamp() = 0;
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virtual u64& Timestamp() = 0;
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@ -337,25 +349,23 @@ public:
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//else
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//else
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// Cycles += numC + numD;
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// Cycles += numC + numD;
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}
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}
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#ifdef INTERLOCK
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// fetch the value of a register while handling any interlock cycles
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// fetch the value of a register while handling any interlock cycles
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inline u32 GetReg(const u32 reg, const u32 delay = 0) override
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inline u32 GetReg(const u32 reg, const u32 delay = 0) override
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{
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{
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#ifdef INTERLOCK
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if (InterlockTimestamp[reg] > (Timestamp() + delay))
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if (InterlockTimestamp[reg] > (Timestamp() + delay))
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Timestamp() = InterlockTimestamp[reg] - delay;
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Timestamp() = InterlockTimestamp[reg] - delay;
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#endif
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return R[reg];
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return R[reg];
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}
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}
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// Must be called after all of an instruction's cycles are calculated!!!
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// Must be called after all of an instruction's cycles are calculated!!!
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inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override
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inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override
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{
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{
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#ifdef INTERLOCK
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InterlockTimestamp[reg] = cycles + Timestamp() + Cycles;
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InterlockTimestamp[reg] = cycles + Timestamp() + Cycles;
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//InterlockType[reg] = type;
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//InterlockType[reg] = type;
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#endif
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}
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}
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#endif
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u64& Timestamp() override;
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u64& Timestamp() override;
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@ -474,6 +484,7 @@ public:
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void AddCycles_CDI() override;
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void AddCycles_CDI() override;
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void AddCycles_CD() override;
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void AddCycles_CD() override;
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#ifdef INTERLOCK
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// fetch the value of a register while handling any interlock cycles
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// fetch the value of a register while handling any interlock cycles
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inline u32 GetReg(const u32 reg, const u32 delay = 0) override
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inline u32 GetReg(const u32 reg, const u32 delay = 0) override
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{
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{
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@ -482,6 +493,7 @@ public:
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// Must be called after all of an instruction's cycles are calculated!!!
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// Must be called after all of an instruction's cycles are calculated!!!
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inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override{}
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inline void SetCycles_L(const u32 reg, const u32 cycles, const u32 type) override{}
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#endif
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u64& Timestamp() override;
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u64& Timestamp() override;
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protected:
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protected:
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