piwalker/melonDS
1
0
Fork 0
mirror of https://github.com/melonDS-emu/melonDS.git synced 2025-07-23 06:10:03 -06:00
Code Issues Packages Projects Releases Wiki Activity

Refactor NDS and DSi to be objects (#1893)

Browse Source 
* First crack at refactoring NDS and DSi into objects

- Remove all global/`static` variables in `NDS` and related classes
- Rely more on virtual dispatch when we need to pick methods at runtime
- Pass `NDS&` or `DSi&` to its constituent components where necessary
- Introduce some headers or move some definitions to break `#include` cycles

* Refactor the frontend to accommodate the core's changes

* Move up `SchedList`'s declaration

- Move it to before the components are initialized so the `map`s inside are initialized
- Fields in C++ are initialized in the order they're declared

* Fix a crash when allocating memory

* Fix JIT-free builds

* Fix GDB-free builds

* Fix Linux builds

- Explicitly qualify some member types in NDS, since they share the same name as their classes

* Remove an unnecessary template argument

- This was causing the build to fail on macOS

* Fix ARM and Android builds

* Rename `Constants.h` to `MemConstants.h`

* Add `NDS::IsRunning()`

* Use an `#include` guard instead of `#pragma once`
This commit is contained in:
Jesse Talavera-Greenberg
2023-11-28 17:16:41 -05:00
committed by GitHub
parent c84cb17462
commit e973236203
73 changed files with 3537 additions and 3176 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/CP15.cpp
View File

@ -124,7 +124,7 @@ void ARMv5::UpdateDTCMSetting()
if (newDTCMBase != DTCMBase || newDTCMMask != DTCMMask)
{
JIT.Memory.RemapDTCM(newDTCMBase, newDTCMSize);
NDS.JIT.Memory.RemapDTCM(newDTCMBase, newDTCMSize);
DTCMBase = newDTCMBase;
DTCMMask = newDTCMMask;
}
@ -295,7 +295,7 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
for (u32 i = addrstart; i < addrend; i++)
{
u8 pu = PU_Map[i];
u8* bustimings = NDS::ARM9MemTimings[i >> 2];
u8* bustimings = NDS.ARM9MemTimings[i >> 2];
if (pu & 0x40)
{
@ -303,7 +303,7 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
}
else
{
MemTimings[i][0] = bustimings[2] << NDS::ARM9ClockShift;
MemTimings[i][0] = bustimings[2] << NDS.ARM9ClockShift;
}
if (pu & 0x10)
@ -314,9 +314,9 @@ void ARMv5::UpdateRegionTimings(u32 addrstart, u32 addrend)
}
else
{
MemTimings[i][1] = bustimings[0] << NDS::ARM9ClockShift;
MemTimings[i][2] = bustimings[2] << NDS::ARM9ClockShift;
MemTimings[i][3] = bustimings[3] << NDS::ARM9ClockShift;
MemTimings[i][1] = bustimings[0] << NDS.ARM9ClockShift;
MemTimings[i][2] = bustimings[2] << NDS.ARM9ClockShift;
MemTimings[i][3] = bustimings[3] << NDS.ARM9ClockShift;
}
}
}
@ -388,14 +388,14 @@ void ARMv5::ICacheLookup(u32 addr)
else
{
for (int i = 0; i < 32; i+=4)
*(u32*)&ptr[i] = NDS::ARM9Read32(addr+i);
*(u32*)&ptr[i] = NDS.ARM9Read32(addr+i);
}
ICacheTags[line] = tag;
// ouch :/
//printf("cache miss %08X: %d/%d\n", addr, NDS::ARM9MemTimings[addr >> 14][2], NDS::ARM9MemTimings[addr >> 14][3]);
CodeCycles = (NDS::ARM9MemTimings[addr >> 14][2] + (NDS::ARM9MemTimings[addr >> 14][3] * 7)) << NDS::ARM9ClockShift;
CodeCycles = (NDS.ARM9MemTimings[addr >> 14][2] + (NDS.ARM9MemTimings[addr >> 14][3] * 7)) << NDS.ARM9ClockShift;
CurICacheLine = ptr;
}
@ -923,7 +923,7 @@ void ARMv5::DataWrite8(u32 addr, u8 val)
{
DataCycles = 1;
*(u8*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
}
if ((addr & DTCMMask) == DTCMBase)
@ -953,7 +953,7 @@ void ARMv5::DataWrite16(u32 addr, u16 val)
{
DataCycles = 1;
*(u16*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
}
if ((addr & DTCMMask) == DTCMBase)
@ -983,7 +983,7 @@ void ARMv5::DataWrite32(u32 addr, u32 val)
{
DataCycles = 1;
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
return;
}
if ((addr & DTCMMask) == DTCMBase)
@ -1006,7 +1006,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
DataCycles += 1;
*(u32*)&ITCM[addr & (ITCMPhysicalSize - 1)] = val;
#ifdef JIT_ENABLED
JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(addr);
#endif
return;
}
@ -1021,7 +1021,7 @@ void ARMv5::DataWrite32S(u32 addr, u32 val)
DataCycles += MemTimings[addr >> 12][3];
}
void ARMv5::GetCodeMemRegion(u32 addr, NDS::MemRegion* region)
void ARMv5::GetCodeMemRegion(u32 addr, MemRegion* region)
{
/*if (addr < ITCMSize)
{
@ -1030,7 +1030,7 @@ void ARMv5::GetCodeMemRegion(u32 addr, NDS::MemRegion* region)
return;
}*/
GetMemRegion(addr, false, &CodeMem);
NDS.ARM9GetMemRegion(addr, false, &CodeMem);
}
}