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improve interlock emulation

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add cycles to the instruction execution time rather than the timestamp directly.
This commit is contained in:
Jaklyy
2024-07-04 12:58:58 -04:00
parent bd1665c1d3
commit ea429a1b8d
2 changed files with 11 additions and 8 deletions
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9
src/ARM.cpp
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@ -696,6 +696,7 @@ void ARMv5::Execute()
NDS.ARM9Timestamp += Cycles;
Cycles = 0;
CyclesILed = 0;
}
if (Halted == 2)
@ -1262,7 +1263,7 @@ bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
void ARMv5::AddCycles_CD_STR()
{
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 numD = DataCycles + CyclesILed;
s32 early;
if (DataRegion == Mem9_ITCM)
@ -1287,7 +1288,7 @@ void ARMv5::AddCycles_CD_STR()
void ARMv5::AddCycles_CD_STM()
{
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 numD = DataCycles + CyclesILed;
s32 early;
if (DataRegion == Mem9_ITCM)
@ -1313,7 +1314,7 @@ void ARMv5::AddCycles_CDI_LDR()
{
// LDR cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 numD = DataCycles + CyclesILed;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early;
@ -1340,7 +1341,7 @@ void ARMv5::AddCycles_CDI_LDM()
{
// LDM cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles;
s32 numD = DataCycles + CyclesILed;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early;