mirror of
https://github.com/melonDS-emu/melonDS.git
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JIT: implemented most ALU instructions
This commit is contained in:
RSDuck
@ -8,18 +8,16 @@ using namespace Gen;
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namespace ARMJIT
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{
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const int RegCache::NativeRegAllocOrder[] = {(int)RBX, (int)RSI, (int)RDI, (int)R12, (int)R13};
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const int RegCache::NativeRegsCount = 5;
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template <>
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const X64Reg RegCache<Compiler, X64Reg>::NativeRegAllocOrder[] = {RBX, RSI, RDI, R12, R13};
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template <>
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const int RegCache<Compiler, X64Reg>::NativeRegsAvailable = 5;
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Compiler::Compiler()
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{
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AllocCodeSpace(1024 * 1024 * 4);
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}
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typedef void (Compiler::*CompileFunc)();
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typedef void (*InterpretFunc)(ARM*);
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void Compiler::LoadCPSR()
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{
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assert(!CPSRDirty);
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@ -36,6 +34,19 @@ void Compiler::SaveCPSR()
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}
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}
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void Compiler::LoadReg(int reg, X64Reg nativeReg)
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{
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if (reg != 15)
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MOV(32, R(nativeReg), MDisp(RCPU, offsetof(ARM, R[reg])));
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else
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MOV(32, R(nativeReg), Imm32(R15));
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}
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void Compiler::UnloadReg(int reg, X64Reg nativeReg)
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{
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MOV(32, MDisp(RCPU, offsetof(ARM, R[reg])), R(nativeReg));
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}
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CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrsCount)
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{
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if (IsAlmostFull())
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@ -58,12 +69,18 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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LoadCPSR();
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// TODO: this is ugly as a whole, do better
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RegCache = ARMJIT::RegCache<Compiler, X64Reg>(this, instrs, instrsCount);
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for (int i = 0; i < instrsCount; i++)
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{
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R15 += Thumb ? 2 : 4;
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CurrentInstr = instrs[i];
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CompileFunc comp = NULL;
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CompileFunc comp = GetCompFunc(CurrentInstr.Info.Kind);
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if (CurrentInstr.Info.Branches())
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comp = NULL;
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if (comp == NULL || i == instrsCount - 1)
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{
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@ -79,6 +96,11 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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SaveCPSR();
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}
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if (comp != NULL)
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RegCache.Prepare(i);
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else
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RegCache.Flush();
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if (Thumb)
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{
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if (comp == NULL)
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@ -89,8 +111,7 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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ABI_CallFunction(ARMInterpreter::THUMBInstrTable[icode]);
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}
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else
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{
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}
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(this->*comp)();
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}
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else
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{
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@ -101,7 +122,7 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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ABI_CallFunction(ARMInterpreter::A_BLX_IMM);
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}
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else if (cond == 0xF)
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AddCycles_C();
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Comp_AddCycles_C();
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else
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{
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FixupBranch skipExecute;
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@ -115,17 +136,17 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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MOV(32, R(RSCRATCH), Imm32(1));
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SHL(32, R(RSCRATCH), R(RSCRATCH3));
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TEST(32, R(RSCRATCH), Imm32(ARM::ConditionTable[cond]));
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skipExecute = J_CC(CC_Z);
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}
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else
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{
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// could have used a LUT, but then where would be the fun?
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BT(32, R(RCPSR), Imm8(28 + ((~(cond >> 1) & 1) << 1 | (cond >> 2 & 1) ^ (cond >> 1 & 1))));
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skipExecute = J_CC(cond & 1 ? CC_C : CC_NC);
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}
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}
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if (comp == NULL)
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@ -136,8 +157,7 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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ABI_CallFunction(ARMInterpreter::ARMInstrTable[icode]);
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}
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else
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{
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}
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(this->*comp)();
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FixupBranch skipFailed;
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if (CurrentInstr.Cond() < 0xE)
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@ -145,7 +165,7 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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skipFailed = J();
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SetJumpTarget(skipExecute);
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AddCycles_C();
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Comp_AddCycles_C();
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SetJumpTarget(skipFailed);
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}
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@ -155,13 +175,14 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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/*
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we don't need to collect the interpreted cycles,
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since all functions only add to it, the dispatcher
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can take care of it.
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takes care of it.
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*/
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if (comp == NULL && i != instrsCount - 1)
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LoadCPSR();
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}
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RegCache.Flush();
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SaveCPSR();
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LEA(32, RAX, MDisp(RCycles, ConstantCycles));
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@ -172,42 +193,57 @@ CompiledBlock Compiler::CompileBlock(ARM* cpu, FetchedInstr instrs[], int instrs
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return res;
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}
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void Compiler::Compile(RegCache& regs, const FetchedInstr& instr)
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CompileFunc Compiler::GetCompFunc(int kind)
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{
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// this might look like waste of space, so many repeatitions, but it's invaluable for debugging.
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// see ARMInstrInfo.h for the order
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const CompileFunc A_Comp[ARMInstrInfo::ak_Count] =
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{
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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// AND
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// EOR
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// SUB
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// RSB
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// ADD
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// ADC
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// SBC
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// RSC
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// ORR
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// MOV
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A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp,
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A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp,
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// BIC
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith, A_Comp_Arith,
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// MVN
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A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp,
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A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp, A_Comp_MovOp,
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// TST
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A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp,
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// TEQ
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A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp,
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// CMP
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A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp,
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// CMN
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A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp, A_Comp_CmpOp,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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@ -227,21 +263,34 @@ void Compiler::Compile(RegCache& regs, const FetchedInstr& instr)
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};
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const CompileFunc T_Comp[ARMInstrInfo::tk_Count] = {
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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// Shift imm
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T_Comp_ShiftImm, T_Comp_ShiftImm, T_Comp_ShiftImm,
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// Three operand ADD/SUB
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T_Comp_AddSub_, T_Comp_AddSub_, T_Comp_AddSub_, T_Comp_AddSub_,
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// 8 bit imm
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T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8, T_Comp_ALU_Imm8,
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// general ALU
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, T_Comp_ALU, T_Comp_ALU, T_Comp_ALU,
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T_Comp_ALU, NULL, T_Comp_ALU, T_Comp_ALU,
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// hi reg
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T_Comp_ALU_HiReg, T_Comp_ALU_HiReg, T_Comp_ALU_HiReg,
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// pc/sp relative
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NULL, NULL, NULL,
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// mem...
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NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL
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};
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return Thumb ? T_Comp[kind] : A_Comp[kind];
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}
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void Compiler::AddCycles_C()
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void Compiler::Comp_AddCycles_C()
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{
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s32 cycles = Num ?
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NDS::ARM7MemTimings[CurrentInstr.CodeCycles][Thumb ? 1 : 3]
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@ -253,80 +302,16 @@ void Compiler::AddCycles_C()
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ConstantCycles += cycles;
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}
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// may uses RSCRATCH for op2 and RSCRATCH2 for the carryValue
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OpArg Compiler::Comp_ShiftRegImm(int op, int amount, Gen::X64Reg rm, bool S, bool& carryUsed)
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{
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carryUsed = true;
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switch (op)
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{
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case 0: // LSL
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if (amount > 0)
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{
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MOV(32, R(RSCRATCH), R(rm));
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SHL(32, R(RSCRATCH), Imm8(amount));
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if (S)
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SETcc(CC_C, R(RSCRATCH2));
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return R(RSCRATCH);
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}
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else
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{
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carryUsed = false;
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return R(rm);
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}
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case 1: // LSR
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if (amount > 0)
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{
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MOV(32, R(RSCRATCH), R(rm));
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SHR(32, R(RSCRATCH), Imm8(amount));
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if (S)
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SETcc(CC_C, R(RSCRATCH2));
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return R(RSCRATCH);
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}
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else
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{
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if (S)
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{
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MOV(32, R(RSCRATCH2), R(rm));
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SHR(32, R(RSCRATCH2), Imm8(31));
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}
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return Imm32(0);
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}
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case 2: // ASR
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MOV(32, R(RSCRATCH), R(rm));
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SAR(32, R(RSCRATCH), Imm8(amount ? amount : 31));
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if (S)
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{
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if (amount == 0)
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{
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MOV(32, R(RSCRATCH2), R(rm));
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SHR(32, R(RSCRATCH2), Imm8(31));
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}
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else
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SETcc(CC_C, R(RSCRATCH2));
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}
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return R(RSCRATCH);
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case 3: // ROR
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if (amount > 0)
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{
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MOV(32, R(RSCRATCH), R(rm));
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ROR_(32, R(RSCRATCH), Imm8(amount));
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}
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else
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{
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BT(32, R(RCPSR), Imm8(29));
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MOV(32, R(RSCRATCH), R(rm));
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RCR(32, R(RSCRATCH), Imm8(1));
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}
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if (S)
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SETcc(CC_C, R(RSCRATCH2));
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return R(RSCRATCH);
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}
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}
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void Compiler::A_Comp_ALU(const FetchedInstr& instr)
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void Compiler::Comp_AddCycles_CI(u32 i)
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{
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s32 cycles = (Num ?
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NDS::ARM7MemTimings[CurrentInstr.CodeCycles][Thumb ? 0 : 2]
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: ((R15 & 0x2) ? 0 : CurrentInstr.CodeCycles)) + i;
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if (CurrentInstr.Cond() < 0xE)
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ADD(32, R(RCycles), Imm8(cycles));
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else
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ConstantCycles += cycles;
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||||
}
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user