Commit Graph

30 Commits

Author SHA1 Message Date
d1eff4acf5 update copyright headers (about time) 2025-05-27 00:31:37 +02:00
8fc403cdad update copyright headers 2024-06-15 17:01:19 +02:00
346dd4006e Move all core types into namespaces (#1886)
* Reorganize namespaces

- Most types are now moved into the `melonDS` namespace
- Only good chance to do this for a while, since a big refactor is next

* Fix the build
2023-11-25 18:32:09 +01:00
544fefa27f Refactor the JIT to be object-oriented (#1879)
* Move TinyVector to a new file

- So it's less sensitive to #include ordering

* Forgot to include assert.h

* Refactor ARMJIT_Memory into an object

* Oops, forgot a declaration

* Refactor ARMJIT to be contained in an object

* Remove an unused function declaration

* Add a missing #include

* Remove a now-unused global

* Use ARMJIT_Memory's own memory access functions

* Fix some omissions in the ARM JIT

* Move libandroid to be a member of ARMJIT_Memory instead of a global

* Default-initialize most fields in ARMJIT_Compiler.h

* Define NOOP_IF_NO_JIT

* Finish refactoring the JIT to be object-oriented
2023-11-18 16:40:54 +01:00
ac38faef14 update copyright years 2023-11-04 00:21:46 +01:00
9394dde67a fix copyright headers 2022-03-07 21:08:54 +01:00
35cc79787d update copyright headers 2022-01-09 02:15:50 +01:00
c1dcd585be decouple JIT from Config. bahahahahah 2021-11-17 18:15:50 +01:00
aa430608e7 support allocating more registers for aarch64 JIT
also some minor fixes for the x64 JIT as well
2021-06-29 22:25:43 +02:00
436b3c4c1d update copyright year and add missing GPL headers 2021-03-12 20:07:40 +01:00
887ad27ed8 implement carry setting ALU op with imm 2020-07-25 22:08:43 +02:00
e335a8ca76 first steps in bringing over the JIT refactor/fastmem 2020-06-16 12:11:19 +02:00
0f53a34551 rewrite JIT memory emulation 2020-05-09 00:45:05 +02:00
a9dd6e30ad implement msr and mrs for the x64 JIT 2020-04-26 13:05:18 +02:00
d6cc7de6c4 move ARM64 JIT backend here 2020-04-26 13:05:09 +02:00
9b98b8816a improve nop handling and proper behaviour for LDM^
fixes dslinux
2020-04-26 13:05:08 +02:00
81f38c14be integrate changes from ARM64 backend and more
- better handle LDM/STM in reg alloc
- unify Halted and IRQ in anticipation for branch inlining
- literal optimisations can be disabled in gui
- jit blocks follow simple returns
- fix idle loop detection
- break jit blocks on IRQ (fixes saving in Pokemon White)
2020-04-26 13:05:05 +02:00
aa23f21b8d decrease jit block cache address granularity
fixes Dragon Quest IX
move code with side effects out of assert, fixes release build
(thanks to m4wx for this one)
also remove some leftovers of jit pipelining
2020-04-26 13:05:05 +02:00
a687be9879 new block cache and much more...
- more reliable code invalidation detection
- blocks aren't stopped at any branch, but are being followed
if possible to get larger blocks
- idle loop recognition
- optimised literal loads, load/store cycle counting
 and loads/stores from constant addresses
2020-04-26 13:05:03 +02:00
2ef776883f more fixes for flag optimisation
+ small cycle counting optimisation
2020-04-26 13:05:02 +02:00
ea562d2fec fixes for flag optimisation 2020-04-26 13:05:01 +02:00
5ea91b8a03 optimise away unneeded flag sets
- especially useful for thumb code and larger max block sizes
- can still be improved upon
2020-04-26 13:05:00 +02:00
ec21172cd9 fix register alloc for half word loads
fixes Mega Man Star Force 2 with cheat applied
it probably used a pc relative load which were interpreted as branches
2020-04-26 13:04:58 +02:00
4a0f6b3b4b jit: fix thumb hi reg alu and mcr halt
+ mcr/mrc aren't always, msr_imm is never unk on ARM7
2020-04-26 13:03:10 +02:00
be8846e31a jit: fix misc static branch things 2020-04-26 13:03:08 +02:00
8ddc4d5904 jit: fix BLX_reg with rn=lr 2020-04-26 13:03:07 +02:00
c58fdbd66b jit: branch instructions 2020-04-26 13:02:58 +02:00
ff97211114 jit: thumb block transfer working
also pc and sp relative loads and some refactoring
2020-04-26 13:02:57 +02:00
2c44bf927c JIT: most mem instructions working
+ branching
2020-04-26 13:02:57 +02:00
c5c342c009 JIT: base
all instructions are interpreted
2020-04-26 13:02:53 +02:00