35cc79787d
update copyright headers
2022-01-09 02:15:50 +01:00
bfe50e41b4
MCR/MRC aren't available in user mode
2021-10-28 19:47:26 +02:00
9d82826cdb
fix some gaps in CPU modes
...
* non-defined CPU modes are actually possible
* bit4 of all PSRs is forced to one (modes 00-0F aren't possible)
* modes 14/15/16 and 18/19/1A share a SPSR with modes 17 and 1B respectively (but they don't share the register banks)
* modes 10 and 1C/1D/1E don't have a SPSR (MRS returns the CPSR always)
2021-10-28 19:45:32 +02:00
436b3c4c1d
update copyright year and add missing GPL headers
2021-03-12 20:07:40 +01:00
83f8e11bc1
update copyright years
2020-02-14 20:18:08 +01:00
b0efde8bf7
also, update copyright name
2019-01-22 15:58:29 +01:00
86dae1a25c
make this other branch where we're going to actually make it usable
...
but it'll be a gross hack
2018-12-08 20:27:00 +01:00
0b1c2f9691
begin PU work
2018-12-04 18:32:19 +01:00
172fb4876a
begin work on general timing renovation. way shitty because it behaves as if caches were off, so everything will be slow as shit.
2018-12-04 17:54:10 +01:00
fea7955675
fixor copyright years.
2018-09-15 02:32:13 +02:00
49f8aec656
fix some shit
2017-06-13 17:44:35 +02:00
3499949129
* send undefined instructions to the proper exception handler
...
* make ARM9-only instructions fail on ARM7
2017-06-13 15:09:39 +02:00
8a4ed8f41c
reorganize repo, move shit around
2017-03-16 23:01:22 +01:00
