8 Commits

Author	SHA1	Message	Date
RSDuck	d74b15eecc	jit: fix thumb hi reg alu and mcr halt ... + mcr/mrc aren't always, msr_imm is never unk on ARM7	2020-06-16 11:54:06 +02:00
RSDuck	0ff79ea2ad	jit: fix linux	2020-06-16 11:53:11 +02:00
RSDuck	9336fcbbe6	jit: SMULL and SMLAL	2020-06-16 11:53:10 +02:00
RSDuck	f22521a43d	jit: LDM/STM finally(!) working + MUL, MLA and CLZ	2020-06-16 11:53:10 +02:00
RSDuck	10e386fe50	JIT: most mem instructions working ... + branching	2020-06-16 11:53:08 +02:00
RSDuck	550e6b86d2	JIT: compilation of word load and store	2020-06-16 11:53:07 +02:00
RSDuck	ea98a44e1e	jit: correct cycle counting for thumb shift by reg	2020-06-16 11:53:06 +02:00
RSDuck	2f6b46fd4f	JIT: implemented most ALU instructions	2020-06-16 11:53:06 +02:00