70 Commits

Author	SHA1	Message	Date
RSDuck	5e443e7962	remove unneeded dolphin code, C++11 static_assert	2020-04-26 13:04:57 +02:00
RSDuck	f31976fed0	jit: fix RSC	2020-04-26 13:03:12 +02:00
RSDuck	4a0f6b3b4b	jit: fix thumb hi reg alu and mcr halt ... + mcr/mrc aren't always, msr_imm is never unk on ARM7	2020-04-26 13:03:10 +02:00
RSDuck	9d180c7bbc	jit: decrease blockcache AddrMapping size for ARM9	2020-04-26 13:03:09 +02:00
RSDuck	be8846e31a	jit: fix misc static branch things	2020-04-26 13:03:08 +02:00
RSDuck	54985be157	jit: LDM/STM keep proper stack alignment	2020-04-26 13:03:08 +02:00
RSDuck	8ddc4d5904	jit: fix BLX_reg with rn=lr	2020-04-26 13:03:07 +02:00
RSDuck	411fb57c07	jit: add compile option	2020-04-26 13:03:06 +02:00
RSDuck	9d76d63af5	jit: make everything configurable	2020-04-26 13:03:03 +02:00
RSDuck	dcf6e1cad2	jit: fix linux	2020-04-26 13:03:01 +02:00
RSDuck	6f0dcad4f6	jit: fix wrongly placed const	2020-04-26 13:03:01 +02:00
RSDuck	9b3c14b58a	jit: SMULL and SMLAL	2020-04-26 13:03:00 +02:00
RSDuck	2efab201e9	jit: LDM/STM finally(!) working + MUL, MLA and CLZ	2020-04-26 13:02:59 +02:00
RSDuck	c58fdbd66b	jit: branch instructions	2020-04-26 13:02:58 +02:00
RSDuck	ff97211114	jit: thumb block transfer working ... also pc and sp relative loads and some refactoring	2020-04-26 13:02:57 +02:00
RSDuck	2c44bf927c	JIT: most mem instructions working ... + branching	2020-04-26 13:02:57 +02:00
RSDuck	5f932cdf48	JIT: compilation of word load and store	2020-04-26 13:02:56 +02:00
RSDuck	ff901141e7	jit: correct cycle counting for thumb shift by reg	2020-04-26 13:02:55 +02:00
RSDuck	ebce9f035f	JIT: implemented most ALU instructions	2020-04-26 13:02:55 +02:00
RSDuck	c5c342c009	JIT: base ... all instructions are interpreted	2020-04-26 13:02:53 +02:00