mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 14:19:55 -06:00
5ea91b8a03
- especially useful for thumb code and larger max block sizes - can still be improved upon
150 lines
3.7 KiB
C++
150 lines
3.7 KiB
C++
#ifndef ARMJIT_H
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#define ARMJIT_H
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#include "types.h"
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#include "ARM.h"
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#include "ARM_InstrInfo.h"
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namespace ARMJIT
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{
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typedef u32 (*CompiledBlock)();
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struct FetchedInstr
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{
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u32 A_Reg(int pos) const
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{
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return (Instr >> pos) & 0xF;
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}
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u32 T_Reg(int pos) const
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{
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return (Instr >> pos) & 0x7;
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}
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u32 Cond() const
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{
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return Instr >> 28;
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}
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u8 SetFlags;
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u32 Instr;
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u32 NextInstr[2];
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u8 CodeCycles;
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ARMInstrInfo::Info Info;
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};
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/*
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Copied from DeSmuME
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Some names where changed to match the nomenclature of melonDS
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Since it's nowhere explained and atleast I needed some time to get behind it,
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here's a summary on how it works:
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more or less all memory locations from which code can be executed are
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represented by an array of function pointers, which point to null or
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a function which executes a block instructions starting from there.
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The most significant 4 bits of each address is ignored. This 28 bit space is
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divided into 0x2000 32 KB for ARM9 and 0x4000 16 KB for ARM7, each of which
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a pointer to the relevant place inside the afore mentioned arrays. 32 and 16 KB
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are the sizes of the smallest contigous memory region mapped to the respective CPU.
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Because ARM addresses are always aligned to 4 bytes and Thumb to a 2 byte boundary,
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we only need every second half word to be adressable.
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In case a memory write hits mapped memory, the function block at this
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address is set to null, so it's recompiled the next time it's executed.
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This method has disadvantages, namely that only writing to the
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first instruction of a block marks it as invalid and that memory remapping
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(SWRAM and VRAM) isn't taken into account.
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*/
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struct BlockCache
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{
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CompiledBlock* AddrMapping9[0x2000] = {0};
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CompiledBlock* AddrMapping7[0x4000] = {0};
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CompiledBlock MainRAM[4*1024*1024/2];
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CompiledBlock SWRAM[0x8000/2]; // Shared working RAM
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CompiledBlock ARM9_ITCM[0x8000/2];
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CompiledBlock ARM9_LCDC[0xA4000/2];
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CompiledBlock ARM9_BIOS[0x8000/2];
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CompiledBlock ARM7_BIOS[0x4000/2];
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CompiledBlock ARM7_WRAM[0x10000/2]; // dedicated ARM7 WRAM
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CompiledBlock ARM7_WVRAM[0x40000/2]; // VRAM allocated as Working RAM
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};
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extern BlockCache cache;
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template <u32 num>
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inline bool IsMapped(u32 addr)
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{
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if (num == 0)
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return cache.AddrMapping9[(addr & 0xFFFFFFF) >> 15];
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else
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return cache.AddrMapping7[(addr & 0xFFFFFFF) >> 14];
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}
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template <u32 num>
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inline CompiledBlock LookUpBlock(u32 addr)
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{
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if (num == 0)
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return cache.AddrMapping9[(addr & 0xFFFFFFF) >> 15][(addr & 0x7FFF) >> 1];
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else
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return cache.AddrMapping7[(addr & 0xFFFFFFF) >> 14][(addr & 0x3FFF) >> 1];
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}
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template <u32 num>
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inline void Invalidate16(u32 addr)
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{
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if (IsMapped<num>(addr))
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{
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if (num == 0)
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cache.AddrMapping9[(addr & 0xFFFFFFF) >> 15][(addr & 0x7FFF) >> 1] = NULL;
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else
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cache.AddrMapping7[(addr & 0xFFFFFFF) >> 14][(addr & 0x3FFF) >> 1] = NULL;
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}
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}
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template <u32 num>
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inline void Invalidate32(u32 addr)
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{
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if (IsMapped<num>(addr))
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{
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if (num == 0)
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{
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CompiledBlock* page = cache.AddrMapping9[(addr & 0xFFFFFFF) >> 15];
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page[(addr & 0x7FFF) >> 1] = NULL;
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page[((addr + 2) & 0x7FFF) >> 1] = NULL;
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}
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else
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{
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CompiledBlock* page = cache.AddrMapping7[(addr & 0xFFFFFFF) >> 14];
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page[(addr & 0x3FFF) >> 1] = NULL;
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page[((addr + 2) & 0x3FFF) >> 1] = NULL;
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}
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}
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}
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template <u32 num>
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inline void InsertBlock(u32 addr, CompiledBlock func)
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{
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if (num == 0)
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cache.AddrMapping9[(addr & 0xFFFFFFF) >> 15][(addr & 0x7FFF) >> 1] = func;
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else
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cache.AddrMapping7[(addr & 0xFFFFFFF) >> 14][(addr & 0x3FFF) >> 1] = func;
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}
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void Init();
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void DeInit();
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CompiledBlock CompileBlock(ARM* cpu);
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void InvalidateBlockCache();
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}
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#endif |