mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2025-07-23 06:10:03 -06:00
600 lines
20 KiB
C++
600 lines
20 KiB
C++
#include "ARMJIT_Compiler.h"
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#include "../GPU.h"
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#include "../Wifi.h"
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namespace NDS
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{
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#define MAIN_RAM_SIZE 0x400000
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extern u8* SWRAM_ARM9;
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extern u32 SWRAM_ARM9Mask;
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extern u8* SWRAM_ARM7;
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extern u32 SWRAM_ARM7Mask;
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extern u8 ARM7WRAM[];
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extern u16 ARM7BIOSProt;
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}
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using namespace Gen;
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namespace ARMJIT
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{
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void* ReadMemFuncs9[16];
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void* ReadMemFuncs7[2][16];
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void* WriteMemFuncs9[16];
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void* WriteMemFuncs7[2][16];
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template <typename T>
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int squeezePointer(T* ptr)
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{
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int truncated = (int)((u64)ptr);
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assert((T*)((u64)truncated) == ptr);
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return truncated;
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}
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u32 ReadVRAM9(u32 addr)
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{
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switch (addr & 0x00E00000)
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{
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case 0x00000000: return GPU::ReadVRAM_ABG<u32>(addr);
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case 0x00200000: return GPU::ReadVRAM_BBG<u32>(addr);
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case 0x00400000: return GPU::ReadVRAM_AOBJ<u32>(addr);
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case 0x00600000: return GPU::ReadVRAM_BOBJ<u32>(addr);
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default: return GPU::ReadVRAM_LCDC<u32>(addr);
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}
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}
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void WriteVRAM9(u32 addr, u32 val)
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{
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switch (addr & 0x00E00000)
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{
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case 0x00000000: GPU::WriteVRAM_ABG<u32>(addr, val); return;
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case 0x00200000: GPU::WriteVRAM_BBG<u32>(addr, val); return;
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case 0x00400000: GPU::WriteVRAM_AOBJ<u32>(addr, val); return;
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case 0x00600000: GPU::WriteVRAM_BOBJ<u32>(addr, val); return;
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default: GPU::WriteVRAM_LCDC<u32>(addr, val); return;
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}
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}
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/*
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R11 - data to write (store only)
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RSCRATCH2 - address
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RSCRATCH3 - code cycles
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*/
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void* Compiler::Gen_MemoryRoutine9(bool store, int size, u32 region)
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{
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AlignCode4();
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void* res = (void*)GetWritableCodePtr();
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if (!store)
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{
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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AND(32, R(RSCRATCH), Imm8(0x3));
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SHL(32, R(RSCRATCH), Imm8(3));
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// enter the shadow realm!
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MOV(32, MDisp(RSP, 8), R(RSCRATCH));
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}
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// cycle counting!
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// this is AddCycles_CDI
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MOV(32, R(R10), R(RSCRATCH2));
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SHR(32, R(R10), Imm8(12));
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MOVZX(32, 8, R10, MComplex(RCPU, R10, SCALE_1, offsetof(ARMv5, MemTimings) + 2));
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LEA(32, RSCRATCH, MComplex(RSCRATCH3, R10, SCALE_1, -6));
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CMP(32, R(R10), R(RSCRATCH3));
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CMOVcc(32, RSCRATCH3, R(R10), CC_G);
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CMP(32, R(RSCRATCH), R(RSCRATCH3));
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CMOVcc(32, RSCRATCH3, R(RSCRATCH), CC_G);
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ADD(32, R(RCycles), R(RSCRATCH3));
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if (!store)
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XOR(32, R(RSCRATCH), R(RSCRATCH));
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AND(32, R(RSCRATCH2), Imm32(~3));
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{
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MOV(32, R(RSCRATCH3), R(RSCRATCH2));
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SUB(32, R(RSCRATCH2), MDisp(RCPU, offsetof(ARMv5, DTCMBase)));
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CMP(32, R(RSCRATCH2), MDisp(RCPU, offsetof(ARMv5, DTCMSize)));
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FixupBranch outsideDTCM = J_CC(CC_AE);
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AND(32, R(RSCRATCH2), Imm32(0x3FFF));
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if (!store)
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{
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH2, SCALE_1, offsetof(ARMv5, DTCM)));
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MOV(32, R(ECX), MDisp(RSP, 8));
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ROR_(32, R(RSCRATCH), R(ECX));
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}
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else
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MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_1, offsetof(ARMv5, DTCM)), R(R11));
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RET();
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SetJumpTarget(outsideDTCM);
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MOV(32, R(RSCRATCH2), R(RSCRATCH3));
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}
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switch (region)
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{
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case 0x00000000:
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case 0x01000000:
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{
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CMP(32, R(RSCRATCH2), MDisp(RCPU, offsetof(ARMv5, ITCMSize)));
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FixupBranch insideITCM = J_CC(CC_B);
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RET();
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SetJumpTarget(insideITCM);
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AND(32, R(RSCRATCH2), Imm32(0x7FFF));
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if (!store)
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MOV(32, R(RSCRATCH), MComplex(RCPU, RSCRATCH2, SCALE_1, offsetof(ARMv5, ITCM)));
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else
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{
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MOV(32, MComplex(RCPU, RSCRATCH2, SCALE_1, offsetof(ARMv5, ITCM)), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.ARM9_ITCM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.ARM9_ITCM) + 8), Imm32(0));
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}
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}
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break;
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case 0x02000000:
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AND(32, R(RSCRATCH2), Imm32(MAIN_RAM_SIZE - 1));
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if (!store)
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(NDS::MainRAM)));
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else
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{
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MOV(32, MDisp(RSCRATCH2, squeezePointer(NDS::MainRAM)), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.MainRAM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.MainRAM) + 8), Imm32(0));
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}
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break;
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case 0x03000000:
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{
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MOV(64, R(RSCRATCH3), M(&NDS::SWRAM_ARM9));
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TEST(64, R(RSCRATCH3), R(RSCRATCH3));
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FixupBranch notMapped = J_CC(CC_Z);
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AND(32, R(RSCRATCH2), M(&NDS::SWRAM_ARM9Mask));
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if (!store)
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MOV(32, R(RSCRATCH), MRegSum(RSCRATCH2, RSCRATCH3));
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else
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{
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MOV(32, MRegSum(RSCRATCH2, RSCRATCH3), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.SWRAM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.SWRAM) + 8), Imm32(0));
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}
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SetJumpTarget(notMapped);
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}
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break;
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case 0x04000000:
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({}, 8, 0);
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ABI_CallFunction(NDS::ARM9IORead32);
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ABI_PopRegistersAndAdjustStack({}, 8, 0);
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}
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else
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{
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MOV(32, R(ABI_PARAM2), R(R11));
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JMP((u8*)NDS::ARM9IOWrite32, true);
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}
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break;
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case 0x05000000:
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{
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MOV(32, R(RSCRATCH), Imm32(1<<1));
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MOV(32, R(RSCRATCH3), Imm32(1<<9));
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TEST(32, R(RSCRATCH2), Imm32(0x400));
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CMOVcc(32, RSCRATCH, R(RSCRATCH3), CC_NZ);
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TEST(16, R(RSCRATCH), M(&NDS::PowerControl9));
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FixupBranch available = J_CC(CC_NZ);
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RET();
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SetJumpTarget(available);
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AND(32, R(RSCRATCH2), Imm32(0x7FF));
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if (!store)
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(GPU::Palette)));
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else
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MOV(32, MDisp(RSCRATCH2, squeezePointer(GPU::Palette)), R(R11));
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}
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break;
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case 0x06000000:
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({}, 8);
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ABI_CallFunction(ReadVRAM9);
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ABI_PopRegistersAndAdjustStack({}, 8);
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}
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else
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{
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MOV(32, R(ABI_PARAM2), R(R11));
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JMP((u8*)WriteVRAM9, true);
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}
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break;
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case 0x07000000:
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{
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MOV(32, R(RSCRATCH), Imm32(1<<1));
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MOV(32, R(RSCRATCH3), Imm32(1<<9));
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TEST(32, R(RSCRATCH2), Imm32(0x400));
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CMOVcc(32, RSCRATCH, R(RSCRATCH3), CC_NZ);
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TEST(16, R(RSCRATCH), M(&NDS::PowerControl9));
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FixupBranch available = J_CC(CC_NZ);
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RET();
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SetJumpTarget(available);
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AND(32, R(RSCRATCH2), Imm32(0x7FF));
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if (!store)
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(GPU::OAM)));
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else
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MOV(32, MDisp(RSCRATCH2, squeezePointer(GPU::OAM)), R(R11));
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}
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break;
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case 0x08000000:
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case 0x09000000:
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case 0x0A000000:
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if (!store)
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MOV(32, R(RSCRATCH), Imm32(0xFFFFFFFF));
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break;
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case 0xFF000000:
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if (!store)
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{
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AND(32, R(RSCRATCH2), Imm32(0xFFF));
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(NDS::ARM9BIOS)));
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}
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break;
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default:
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({}, 8, 0);
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ABI_CallFunction(NDS::ARM9Read32);
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ABI_PopRegistersAndAdjustStack({}, 8, 0);
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}
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else
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{
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MOV(32, R(ABI_PARAM2), R(R11));
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JMP((u8*)NDS::ARM9Write32, true);
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}
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break;
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}
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if (!store)
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{
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MOV(32, R(ECX), MDisp(RSP, 8));
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ROR_(32, R(RSCRATCH), R(ECX));
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}
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RET();
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return res;
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}
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void* Compiler::Gen_MemoryRoutine7(bool store, int size, bool mainRAMCode, u32 region)
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{
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AlignCode4();
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void* res = GetWritableCodePtr();
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if (!store)
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{
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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AND(32, R(RSCRATCH), Imm8(0x3));
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SHL(32, R(RSCRATCH), Imm8(3));
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// enter the shadow realm!
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MOV(32, MDisp(RSP, 8), R(RSCRATCH));
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}
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// AddCycles_CDI
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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SHR(32, R(RSCRATCH), Imm8(15));
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MOVZX(32, 8, RSCRATCH, MDisp(RSCRATCH, squeezePointer(NDS::ARM7MemTimings + 2)));
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if ((region == 0x02000000 && mainRAMCode) || (region != 0x02000000 && !mainRAMCode))
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{
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if (!store && region != 0x02000000)
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LEA(32, RSCRATCH3, MComplex(RSCRATCH, RSCRATCH3, SCALE_1, 1));
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ADD(32, R(RCycles), R(RSCRATCH3));
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}
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else
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{
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if (!store)
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ADD(32, R(region == 0x02000000 ? RSCRATCH2 : RSCRATCH), Imm8(1));
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LEA(32, R10, MComplex(RSCRATCH, RSCRATCH3, SCALE_1, -3));
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CMP(32, R(RSCRATCH3), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(RSCRATCH3), CC_G);
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CMP(32, R(R10), R(RSCRATCH));
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CMOVcc(32, RSCRATCH, R(R10), CC_G);
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ADD(32, R(RCycles), R(RSCRATCH));
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}
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if (!store)
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XOR(32, R(RSCRATCH), R(RSCRATCH));
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AND(32, R(RSCRATCH2), Imm32(~3));
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switch (region)
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{
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case 0x00000000:
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if (!store) {
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CMP(32, R(RSCRATCH2), Imm32(0x4000));
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FixupBranch outsideBIOS1 = J_CC(CC_AE);
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MOV(32, R(RSCRATCH), MDisp(RCPU, offsetof(ARM, R[15])));
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CMP(32, R(RSCRATCH), Imm32(0x4000));
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FixupBranch outsideBIOS2 = J_CC(CC_AE);
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MOV(32, R(RSCRATCH3), M(&NDS::ARM7BIOSProt));
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CMP(32, R(RSCRATCH2), R(RSCRATCH3));
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FixupBranch notDenied1 = J_CC(CC_AE);
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CMP(32, R(RSCRATCH), R(RSCRATCH3));
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FixupBranch notDenied2 = J_CC(CC_B);
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SetJumpTarget(outsideBIOS2);
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MOV(32, R(RSCRATCH), Imm32(0xFFFFFFFF));
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RET();
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SetJumpTarget(notDenied1);
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SetJumpTarget(notDenied2);
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(NDS::ARM7BIOS)));
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MOV(32, R(ECX), MDisp(RSP, 8));
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ROR_(32, R(RSCRATCH), R(ECX));
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RET();
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SetJumpTarget(outsideBIOS1);
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}
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break;
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case 0x02000000:
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AND(32, R(RSCRATCH2), Imm32(MAIN_RAM_SIZE - 1));
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if (!store)
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(NDS::MainRAM)));
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else
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{
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MOV(32, MDisp(RSCRATCH2, squeezePointer(NDS::MainRAM)), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.MainRAM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.MainRAM) + 8), Imm32(0));
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}
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break;
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case 0x03000000:
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{
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TEST(32, R(RSCRATCH2), Imm32(0x800000));
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FixupBranch region = J_CC(CC_NZ);
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MOV(64, R(RSCRATCH), M(&NDS::SWRAM_ARM7));
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TEST(64, R(RSCRATCH), R(RSCRATCH));
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FixupBranch notMapped = J_CC(CC_Z);
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AND(32, R(RSCRATCH2), M(&NDS::SWRAM_ARM7Mask));
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if (!store)
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{
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MOV(32, R(RSCRATCH), MRegSum(RSCRATCH, RSCRATCH2));
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MOV(32, R(ECX), MDisp(RSP, 8));
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ROR_(32, R(RSCRATCH), R(ECX));
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}
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else
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{
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MOV(32, MRegSum(RSCRATCH, RSCRATCH2), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.SWRAM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.SWRAM) + 8), Imm32(0));
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}
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RET();
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SetJumpTarget(region);
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SetJumpTarget(notMapped);
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AND(32, R(RSCRATCH2), Imm32(0xFFFF));
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if (!store)
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MOV(32, R(RSCRATCH), MDisp(RSCRATCH2, squeezePointer(NDS::ARM7WRAM)));
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else
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{
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MOV(32, MDisp(RSCRATCH2, squeezePointer(NDS::ARM7WRAM)), R(R11));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.ARM7_WRAM)), Imm32(0));
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MOV(64, MScaled(RSCRATCH2, SCALE_4, squeezePointer(cache.ARM7_WRAM) + 8), Imm32(0));
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}
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}
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break;
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case 0x04000000:
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{
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TEST(32, R(RSCRATCH2), Imm32(0x800000));
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FixupBranch region = J_CC(CC_NZ);
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({}, 8);
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ABI_CallFunction(NDS::ARM7IORead32);
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ABI_PopRegistersAndAdjustStack({}, 8);
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MOV(32, R(ECX), MDisp(RSP, 8));
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ROR_(32, R(RSCRATCH), R(ECX));
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RET();
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}
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else
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{
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MOV(32, R(ABI_PARAM2), R(R11));
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JMP((u8*)NDS::ARM7IOWrite32, true);
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}
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SetJumpTarget(region);
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({RSCRATCH2}, 8);
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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ABI_CallFunction(Wifi::Read);
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ABI_PopRegistersAndAdjustStack({RSCRATCH2}, 8);
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ADD(32, R(RSCRATCH2), Imm8(2));
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ABI_PushRegistersAndAdjustStack({EAX}, 8);
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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ABI_CallFunction(Wifi::Read);
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MOV(32, R(RSCRATCH2), R(EAX));
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SHL(32, R(RSCRATCH2), Imm8(16));
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ABI_PopRegistersAndAdjustStack({EAX}, 8);
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OR(32, R(EAX), R(RSCRATCH2));
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}
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else
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{
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ABI_PushRegistersAndAdjustStack({RSCRATCH2, R11}, 8);
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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MOVZX(32, 16, ABI_PARAM2, R(R11));
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ABI_CallFunction(Wifi::Write);
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ABI_PopRegistersAndAdjustStack({RSCRATCH2, R11}, 8);
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SHR(32, R(R11), Imm8(16));
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ADD(32, R(RSCRATCH2), Imm8(2));
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ABI_PushRegistersAndAdjustStack({RSCRATCH2, R11}, 8);
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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MOVZX(32, 16, ABI_PARAM2, R(R11));
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ABI_CallFunction(Wifi::Write);
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ABI_PopRegistersAndAdjustStack({RSCRATCH2, R11}, 8);
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}
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}
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break;
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case 0x06000000:
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MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
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if (!store)
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{
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ABI_PushRegistersAndAdjustStack({}, 8);
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ABI_CallFunction(GPU::ReadVRAM_ARM7<u32>);
|
|
ABI_PopRegistersAndAdjustStack({}, 8);
|
|
}
|
|
else
|
|
{
|
|
AND(32, R(ABI_PARAM1), Imm32(0x40000 - 1));
|
|
MOV(64, MScaled(ABI_PARAM1, SCALE_4, squeezePointer(cache.ARM7_WVRAM)), Imm32(0));
|
|
MOV(64, MScaled(ABI_PARAM1, SCALE_4, squeezePointer(cache.ARM7_WVRAM) + 8), Imm32(0));
|
|
MOV(32, R(ABI_PARAM2), R(R11));
|
|
JMP((u8*)GPU::WriteVRAM_ARM7<u32>, true);
|
|
}
|
|
break;
|
|
case 0x08000000:
|
|
case 0x09000000:
|
|
case 0x0A000000:
|
|
if (!store)
|
|
MOV(32, R(RSCRATCH), Imm32(0xFFFFFFFF));
|
|
break;
|
|
/*default:
|
|
ABI_PushRegistersAndAdjustStack({}, 8, 0);
|
|
MOV(32, R(ABI_PARAM1), R(RSCRATCH2));
|
|
ABI_CallFunction(NDS::ARM7Read32);
|
|
ABI_PopRegistersAndAdjustStack({}, 8, 0);
|
|
break;*/
|
|
}
|
|
|
|
if (!store)
|
|
{
|
|
MOV(32, R(ECX), MDisp(RSP, 8));
|
|
ROR_(32, R(RSCRATCH), R(ECX));
|
|
}
|
|
|
|
RET();
|
|
|
|
return res;
|
|
}
|
|
|
|
OpArg Compiler::A_Comp_GetMemWBOffset()
|
|
{
|
|
if (!(CurrentInstr.Instr & (1 << 25)))
|
|
return Imm32(CurrentInstr.Instr & 0xFFF);
|
|
else
|
|
{
|
|
int op = (CurrentInstr.Instr >> 5) & 0x3;
|
|
int amount = (CurrentInstr.Instr >> 7) & 0x1F;
|
|
OpArg rm = MapReg(CurrentInstr.A_Reg(0));
|
|
bool carryUsed;
|
|
return Comp_RegShiftImm(op, amount, rm, false, carryUsed);
|
|
}
|
|
}
|
|
|
|
void Compiler::A_Comp_MemWB()
|
|
{
|
|
OpArg rn = MapReg(CurrentInstr.A_Reg(16));
|
|
OpArg rd = MapReg(CurrentInstr.A_Reg(12));
|
|
bool load = CurrentInstr.Instr & (1 << 20);
|
|
|
|
MOV(32, R(RSCRATCH2), rn);
|
|
if (CurrentInstr.Instr & (1 << 24))
|
|
{
|
|
OpArg offset = A_Comp_GetMemWBOffset();
|
|
if (CurrentInstr.Instr & (1 << 23))
|
|
ADD(32, R(RSCRATCH2), offset);
|
|
else
|
|
SUB(32, R(RSCRATCH2), offset);
|
|
|
|
if (CurrentInstr.Instr & (1 << 21))
|
|
MOV(32, rn, R(RSCRATCH2));
|
|
}
|
|
|
|
u32 cycles = Num ? NDS::ARM7MemTimings[CurrentInstr.CodeCycles][2] : CurrentInstr.CodeCycles;
|
|
MOV(32, R(RSCRATCH3), Imm32(cycles));
|
|
MOV(32, R(RSCRATCH), R(RSCRATCH2));
|
|
SHR(32, R(RSCRATCH), Imm8(24));
|
|
AND(32, R(RSCRATCH), Imm8(0xF));
|
|
void** funcArray;
|
|
if (load)
|
|
funcArray = Num ? ReadMemFuncs7[CodeRegion == 0x02] : ReadMemFuncs9;
|
|
else
|
|
{
|
|
funcArray = Num ? WriteMemFuncs7[CodeRegion == 0x02] : WriteMemFuncs9;
|
|
MOV(32, R(R11), rd);
|
|
}
|
|
CALLptr(MScaled(RSCRATCH, SCALE_8, squeezePointer(funcArray)));
|
|
|
|
if (load)
|
|
MOV(32, R(RSCRATCH2), R(RSCRATCH));
|
|
|
|
if (!(CurrentInstr.Instr & (1 << 24)))
|
|
{
|
|
OpArg offset = A_Comp_GetMemWBOffset();
|
|
|
|
if (CurrentInstr.Instr & (1 << 23))
|
|
ADD(32, rn, offset);
|
|
else
|
|
SUB(32, rn, offset);
|
|
}
|
|
|
|
if (load)
|
|
MOV(32, rd, R(RSCRATCH2));
|
|
}
|
|
|
|
void Compiler::T_Comp_MemReg()
|
|
{
|
|
OpArg rd = MapReg(CurrentInstr.T_Reg(0));
|
|
OpArg rb = MapReg(CurrentInstr.T_Reg(3));
|
|
OpArg ro = MapReg(CurrentInstr.T_Reg(6));
|
|
|
|
int op = (CurrentInstr.Instr >> 10) & 0x3;
|
|
bool load = op & 0x2;
|
|
|
|
MOV(32, R(RSCRATCH2), rb);
|
|
ADD(32, R(RSCRATCH2), ro);
|
|
|
|
u32 cycles = Num ? NDS::ARM7MemTimings[CurrentInstr.CodeCycles][0] : (R15 & 0x2 ? 0 : CurrentInstr.CodeCycles);
|
|
MOV(32, R(RSCRATCH3), Imm32(cycles));
|
|
MOV(32, R(RSCRATCH), R(RSCRATCH2));
|
|
SHR(32, R(RSCRATCH), Imm8(24));
|
|
AND(32, R(RSCRATCH), Imm8(0xF));
|
|
void** funcArray;
|
|
if (load)
|
|
funcArray = Num ? ReadMemFuncs7[CodeRegion == 0x02] : ReadMemFuncs9;
|
|
else
|
|
{
|
|
funcArray = Num ? WriteMemFuncs7[CodeRegion == 0x02] : WriteMemFuncs9;
|
|
MOV(32, R(R11), rd);
|
|
}
|
|
CALLptr(MScaled(RSCRATCH, SCALE_8, squeezePointer(funcArray)));
|
|
|
|
if (load)
|
|
MOV(32, rd, R(RSCRATCH));
|
|
}
|
|
|
|
void Compiler::T_Comp_MemImm()
|
|
{
|
|
// TODO: aufräumen!!!
|
|
OpArg rd = MapReg(CurrentInstr.T_Reg(0));
|
|
OpArg rb = MapReg(CurrentInstr.T_Reg(3));
|
|
|
|
int op = (CurrentInstr.Instr >> 11) & 0x3;
|
|
u32 offset = ((CurrentInstr.Instr >> 6) & 0x1F) * 4;
|
|
bool load = op & 0x1;
|
|
|
|
LEA(32, RSCRATCH2, MDisp(rb.GetSimpleReg(), offset));
|
|
u32 cycles = Num ? NDS::ARM7MemTimings[CurrentInstr.CodeCycles][0] : (R15 & 0x2 ? 0 : CurrentInstr.CodeCycles);
|
|
MOV(32, R(RSCRATCH3), Imm32(cycles));
|
|
MOV(32, R(RSCRATCH), R(RSCRATCH2));
|
|
SHR(32, R(RSCRATCH), Imm8(24));
|
|
AND(32, R(RSCRATCH), Imm8(0xF));
|
|
void** funcArray;
|
|
if (load)
|
|
funcArray = Num ? ReadMemFuncs7[CodeRegion == 0x02] : ReadMemFuncs9;
|
|
else
|
|
{
|
|
funcArray = Num ? WriteMemFuncs7[CodeRegion == 0x02] : WriteMemFuncs9;
|
|
MOV(32, R(R11), rd);
|
|
}
|
|
CALLptr(MScaled(RSCRATCH, SCALE_8, squeezePointer(funcArray)));
|
|
|
|
if (load)
|
|
MOV(32, rd, R(RSCRATCH));
|
|
}
|
|
|
|
} |