mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
128 lines
3.0 KiB
C++
128 lines
3.0 KiB
C++
#include <stdio.h>
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#include "NDS.h"
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#include "ARMInterpreter.h"
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#include "ARMInterpreter_ALU.h"
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#include "ARMInterpreter_Branch.h"
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#include "ARMInterpreter_LoadStore.h"
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namespace ARMInterpreter
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{
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s32 A_UNK(ARM* cpu)
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{
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printf("undefined ARM%d instruction %08X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-8);
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for (int i = 0; i < 16; i++) printf("R%d: %08X\n", i, cpu->R[i]);
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NDS::Halt();
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return 0x7FFFFFFF;
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}
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s32 T_UNK(ARM* cpu)
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{
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printf("undefined THUMB%d instruction %04X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-4);
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NDS::Halt();
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return 0x7FFFFFFF;
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}
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s32 A_MSR_IMM(ARM* cpu)
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{
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u32* psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return 1;
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}
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}
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else
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psr = &cpu->CPSR;
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u32 mask = 0;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000DF;
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if (cpu->CurInstr & (1<<17)) mask |= 0x0000FF00;
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if (cpu->CurInstr & (1<<18)) mask |= 0x00FF0000;
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if (cpu->CurInstr & (1<<19)) mask |= 0xFF000000;
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if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
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u32 val = ROR((cpu->CurInstr & 0xFF), ((cpu->CurInstr >> 7) & 0x1E));
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*psr &= ~mask;
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*psr |= (val & mask);
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return C_S(1);
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}
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s32 A_MSR_REG(ARM* cpu)
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{
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u32* psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return 1;
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}
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}
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else
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psr = &cpu->CPSR;
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u32 mask = 0;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000DF;
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if (cpu->CurInstr & (1<<17)) mask |= 0x0000FF00;
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if (cpu->CurInstr & (1<<18)) mask |= 0x00FF0000;
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if (cpu->CurInstr & (1<<19)) mask |= 0xFF000000;
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if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
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u32 val = cpu->R[cpu->CurInstr & 0xF];
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*psr &= ~mask;
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*psr |= (val & mask);
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return C_S(1);
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}
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s32 A_MRS(ARM* cpu)
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{
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u32 psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = cpu->R_FIQ[7]; break;
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case 0x12: psr = cpu->R_IRQ[2]; break;
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case 0x13: psr = cpu->R_SVC[2]; break;
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case 0x17: psr = cpu->R_ABT[2]; break;
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case 0x1B: psr = cpu->R_UND[2]; break;
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default: printf("bad CPU mode %08X\n", cpu->CPSR); return 1;
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}
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}
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else
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psr = cpu->CPSR;
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cpu->R[(cpu->CurInstr>>12) & 0xF] = psr;
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return C_S(1);
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}
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#define INSTRFUNC_PROTO(x) s32 (*x)(ARM* cpu)
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#include "ARM_InstrTable.h"
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#undef INSTRFUNC_PROTO
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}
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