mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 21:37:42 -07:00
298 lines
7.4 KiB
C++
298 lines
7.4 KiB
C++
/*
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Copyright 2016-2024 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include "NDS.h"
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#include "ARMInterpreter.h"
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#include "ARMInterpreter_ALU.h"
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#include "ARMInterpreter_Branch.h"
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#include "ARMInterpreter_LoadStore.h"
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#include "Platform.h"
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#ifdef GDBSTUB_ENABLED
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#include "debug/GdbStub.h"
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#endif
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namespace melonDS::ARMInterpreter
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{
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using Platform::Log;
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using Platform::LogLevel;
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void A_UNK(ARM* cpu)
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{
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Log(LogLevel::Warn, "undefined ARM%d instruction %08X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-8);
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#ifdef GDBSTUB_ENABLED
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cpu->GdbStub.Enter(true, Gdb::TgtStatus::FaultInsn, cpu->R[15]-8);
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#endif
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//for (int i = 0; i < 16; i++) printf("R%d: %08X\n", i, cpu->R[i]);
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//NDS::Halt();
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u32 oldcpsr = cpu->CPSR;
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cpu->CPSR &= ~0xBF;
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cpu->CPSR |= 0x9B;
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cpu->UpdateMode(oldcpsr, cpu->CPSR);
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cpu->R_UND[2] = oldcpsr;
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cpu->R[14] = cpu->R[15] - 4;
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cpu->JumpTo(cpu->ExceptionBase + 0x04);
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}
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void T_UNK(ARM* cpu)
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{
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Log(LogLevel::Warn, "undefined THUMB%d instruction %04X @ %08X\n", cpu->Num?7:9, cpu->CurInstr, cpu->R[15]-4);
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#ifdef GDBSTUB_ENABLED
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cpu->GdbStub.Enter(true, Gdb::TgtStatus::FaultInsn, cpu->R[15]-4);
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#endif
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//NDS::Halt();
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u32 oldcpsr = cpu->CPSR;
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cpu->CPSR &= ~0xBF;
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cpu->CPSR |= 0x9B;
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cpu->UpdateMode(oldcpsr, cpu->CPSR);
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cpu->R_UND[2] = oldcpsr;
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cpu->R[14] = cpu->R[15] - 2;
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cpu->JumpTo(cpu->ExceptionBase + 0x04);
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}
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void A_MSR_IMM(ARM* cpu)
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{
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u32* psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default:
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cpu->AddCycles_C();
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return;
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}
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}
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else
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psr = &cpu->CPSR;
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u32 oldpsr = *psr;
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u32 mask = 0;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000FF;
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if (cpu->CurInstr & (1<<17)) mask |= 0x0000FF00;
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if (cpu->CurInstr & (1<<18)) mask |= 0x00FF0000;
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if (cpu->CurInstr & (1<<19)) mask |= 0xFF000000;
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if (!(cpu->CurInstr & (1<<22)))
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mask &= 0xFFFFFFDF;
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if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
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u32 val = ROR((cpu->CurInstr & 0xFF), ((cpu->CurInstr >> 7) & 0x1E));
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// bit4 is forced to 1
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val |= 0x00000010;
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*psr &= ~mask;
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*psr |= (val & mask);
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if (!(cpu->CurInstr & (1<<22)))
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cpu->UpdateMode(oldpsr, cpu->CPSR);
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cpu->AddCycles_C();
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}
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void A_MSR_REG(ARM* cpu)
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{
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u32* psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = &cpu->R_FIQ[7]; break;
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case 0x12: psr = &cpu->R_IRQ[2]; break;
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case 0x13: psr = &cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = &cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = &cpu->R_UND[2]; break;
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default:
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cpu->AddCycles_C();
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return;
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}
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}
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else
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psr = &cpu->CPSR;
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u32 oldpsr = *psr;
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u32 mask = 0;
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if (cpu->CurInstr & (1<<16)) mask |= 0x000000FF;
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if (cpu->CurInstr & (1<<17)) mask |= 0x0000FF00;
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if (cpu->CurInstr & (1<<18)) mask |= 0x00FF0000;
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if (cpu->CurInstr & (1<<19)) mask |= 0xFF000000;
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if (!(cpu->CurInstr & (1<<22)))
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mask &= 0xFFFFFFDF;
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if ((cpu->CPSR & 0x1F) == 0x10) mask &= 0xFFFFFF00;
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u32 val = cpu->R[cpu->CurInstr & 0xF];
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// bit4 is forced to 1
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val |= 0x00000010;
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*psr &= ~mask;
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*psr |= (val & mask);
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if (!(cpu->CurInstr & (1<<22)))
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cpu->UpdateMode(oldpsr, cpu->CPSR);
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cpu->AddCycles_C();
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}
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void A_MRS(ARM* cpu)
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{
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u32 psr;
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if (cpu->CurInstr & (1<<22))
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{
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switch (cpu->CPSR & 0x1F)
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{
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case 0x11: psr = cpu->R_FIQ[7]; break;
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case 0x12: psr = cpu->R_IRQ[2]; break;
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case 0x13: psr = cpu->R_SVC[2]; break;
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case 0x14:
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case 0x15:
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case 0x16:
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case 0x17: psr = cpu->R_ABT[2]; break;
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case 0x18:
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case 0x19:
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case 0x1A:
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case 0x1B: psr = cpu->R_UND[2]; break;
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default: psr = cpu->CPSR; break;
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}
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}
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else
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psr = cpu->CPSR;
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cpu->R[(cpu->CurInstr>>12) & 0xF] = psr;
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cpu->AddCycles_C();
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}
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void A_MCR(ARM* cpu)
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{
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if ((cpu->CPSR & 0x1F) == 0x10)
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return A_UNK(cpu);
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u32 cp = (cpu->CurInstr >> 8) & 0xF;
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//u32 op = (cpu->CurInstr >> 21) & 0x7;
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u32 cn = (cpu->CurInstr >> 16) & 0xF;
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u32 cm = cpu->CurInstr & 0xF;
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u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
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if (cpu->Num==0 && cp==15)
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{
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((ARMv5*)cpu)->CP15Write((cn<<8)|(cm<<4)|cpinfo, cpu->R[(cpu->CurInstr>>12)&0xF]);
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}
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else if (cpu->Num==1 && cp==14)
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{
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Log(LogLevel::Debug, "MCR p14,%d,%d,%d on ARM7\n", cn, cm, cpinfo);
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}
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else
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{
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Log(LogLevel::Warn, "bad MCR opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
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return A_UNK(cpu); // TODO: check what kind of exception it really is
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}
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cpu->AddCycles_CI(1 + 1); // TODO: checkme
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}
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void A_MRC(ARM* cpu)
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{
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if ((cpu->CPSR & 0x1F) == 0x10)
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return A_UNK(cpu);
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u32 cp = (cpu->CurInstr >> 8) & 0xF;
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//u32 op = (cpu->CurInstr >> 21) & 0x7;
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u32 cn = (cpu->CurInstr >> 16) & 0xF;
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u32 cm = cpu->CurInstr & 0xF;
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u32 cpinfo = (cpu->CurInstr >> 5) & 0x7;
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if (cpu->Num==0 && cp==15)
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{
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cpu->R[(cpu->CurInstr>>12)&0xF] = ((ARMv5*)cpu)->CP15Read((cn<<8)|(cm<<4)|cpinfo);
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}
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else if (cpu->Num==1 && cp==14)
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{
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Log(LogLevel::Debug, "MRC p14,%d,%d,%d on ARM7\n", cn, cm, cpinfo);
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}
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else
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{
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Log(LogLevel::Warn, "bad MRC opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
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return A_UNK(cpu); // TODO: check what kind of exception it really is
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}
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cpu->AddCycles_CI(2 + 1); // TODO: checkme
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}
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void A_SVC(ARM* cpu)
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{
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u32 oldcpsr = cpu->CPSR;
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cpu->CPSR &= ~0xBF;
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cpu->CPSR |= 0x93;
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cpu->UpdateMode(oldcpsr, cpu->CPSR);
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cpu->R_SVC[2] = oldcpsr;
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cpu->R[14] = cpu->R[15] - 4;
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cpu->JumpTo(cpu->ExceptionBase + 0x08);
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}
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void T_SVC(ARM* cpu)
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{
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u32 oldcpsr = cpu->CPSR;
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cpu->CPSR &= ~0xBF;
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cpu->CPSR |= 0x93;
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cpu->UpdateMode(oldcpsr, cpu->CPSR);
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cpu->R_SVC[2] = oldcpsr;
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cpu->R[14] = cpu->R[15] - 2;
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cpu->JumpTo(cpu->ExceptionBase + 0x08);
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}
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#define INSTRFUNC_PROTO(x) void (*x)(ARM* cpu)
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#include "ARM_InstrTable.h"
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#undef INSTRFUNC_PROTO
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}
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