mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
432 lines
10 KiB
C++
432 lines
10 KiB
C++
/*
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Copyright 2016-2024 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#ifndef ARM_H
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#define ARM_H
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#include <algorithm>
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#include <optional>
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#include "types.h"
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#include "MemRegion.h"
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#include "MemConstants.h"
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#ifdef GDBSTUB_ENABLED
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#include "debug/GdbStub.h"
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#endif
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namespace melonDS
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{
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inline u32 ROR(u32 x, u32 n)
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{
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return (x >> (n&0x1F)) | (x << ((32-n)&0x1F));
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}
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enum
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{
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RWFlags_Nonseq = (1<<5),
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RWFlags_ForceUser = (1<<21),
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};
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enum class CPUExecuteMode : u32
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{
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Interpreter,
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InterpreterGDB,
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#ifdef JIT_ENABLED
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JIT
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#endif
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};
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struct GDBArgs;
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class ARMJIT;
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class GPU;
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class ARMJIT_Memory;
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class NDS;
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class Savestate;
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class ARM
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#ifdef GDBSTUB_ENABLED
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: public Gdb::StubCallbacks
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#endif
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{
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public:
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ARM(u32 num, bool jit, std::optional<GDBArgs> gdb, NDS& nds);
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virtual ~ARM(); // destroy shit
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virtual void Reset();
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virtual void DoSavestate(Savestate* file);
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virtual void FillPipeline() = 0;
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virtual void JumpTo(u32 addr, bool restorecpsr = false) = 0;
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void RestoreCPSR();
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void Halt(u32 halt)
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{
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if (halt==2 && Halted==1) return;
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Halted = halt;
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}
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void NocashPrint(u32 addr) noexcept;
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bool CheckCondition(u32 code) const
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{
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if (code == 0xE) return true;
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if (ConditionTable[code] & (1 << (CPSR>>28))) return true;
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return false;
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}
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void SetC(bool c)
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{
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if (c) CPSR |= 0x20000000;
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else CPSR &= ~0x20000000;
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}
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void SetNZ(bool n, bool z)
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{
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CPSR &= ~0xC0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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}
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void SetNZCV(bool n, bool z, bool c, bool v)
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{
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CPSR &= ~0xF0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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if (c) CPSR |= 0x20000000;
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if (v) CPSR |= 0x10000000;
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}
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inline bool ModeIs(u32 mode) const
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{
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u32 cm = CPSR & 0x1f;
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mode &= 0x1f;
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if (mode == cm) return true;
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if (mode == 0x17) return cm >= 0x14 && cm <= 0x17; // abt
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if (mode == 0x1b) return cm >= 0x18 && cm <= 0x1b; // und
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return false;
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}
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void UpdateMode(u32 oldmode, u32 newmode, bool phony = false);
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void TriggerIRQ();
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void SetupCodeMem(u32 addr);
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virtual void DataRead8(u32 addr, u32* val) = 0;
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virtual void DataRead16(u32 addr, u32* val) = 0;
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virtual void DataRead32(u32 addr, u32* val) = 0;
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virtual void DataRead32S(u32 addr, u32* val) = 0;
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virtual void DataWrite8(u32 addr, u8 val) = 0;
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virtual void DataWrite16(u32 addr, u16 val) = 0;
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virtual void DataWrite32(u32 addr, u32 val) = 0;
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virtual void DataWrite32S(u32 addr, u32 val) = 0;
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virtual void AddCycles_C() = 0;
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virtual void AddCycles_CI(s32 numI) = 0;
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virtual void AddCycles_CDI() = 0;
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virtual void AddCycles_CD() = 0;
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void CheckGdbIncoming();
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u32 Num;
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s32 Cycles;
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union
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{
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struct
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{
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u8 Halted;
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u8 IRQ; // nonzero to trigger IRQ
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u8 IdleLoop;
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};
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u32 StopExecution;
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};
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u32 CodeRegion;
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s32 CodeCycles;
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u32 DataRegion;
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s32 DataCycles;
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u32 R[16]; // heh
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u32 CPSR;
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u32 R_FIQ[8]; // holding SPSR too
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u32 R_SVC[3];
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u32 R_ABT[3];
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u32 R_IRQ[3];
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u32 R_UND[3];
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u32 CurInstr;
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u32 NextInstr[2];
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u32 ExceptionBase;
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MemRegion CodeMem;
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#ifdef JIT_ENABLED
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u32 FastBlockLookupStart, FastBlockLookupSize;
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u64* FastBlockLookup;
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#endif
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static const u32 ConditionTable[16];
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#ifdef GDBSTUB_ENABLED
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Gdb::GdbStub GdbStub;
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#endif
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melonDS::NDS& NDS;
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protected:
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virtual u8 BusRead8(u32 addr) = 0;
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virtual u16 BusRead16(u32 addr) = 0;
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virtual u32 BusRead32(u32 addr) = 0;
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virtual void BusWrite8(u32 addr, u8 val) = 0;
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virtual void BusWrite16(u32 addr, u16 val) = 0;
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virtual void BusWrite32(u32 addr, u32 val) = 0;
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#ifdef GDBSTUB_ENABLED
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bool IsSingleStep;
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bool BreakReq;
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bool BreakOnStartup;
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u16 Port;
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public:
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int GetCPU() const override { return Num ? 7 : 9; }
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u32 ReadReg(Gdb::Register reg) override;
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void WriteReg(Gdb::Register reg, u32 v) override;
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u32 ReadMem(u32 addr, int size) override;
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void WriteMem(u32 addr, int size, u32 v) override;
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void ResetGdb() override;
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int RemoteCmd(const u8* cmd, size_t len) override;
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protected:
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#endif
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void GdbCheckA();
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void GdbCheckB();
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void GdbCheckC();
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};
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class ARMv5 : public ARM
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{
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public:
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ARMv5(melonDS::NDS& nds, std::optional<GDBArgs> gdb, bool jit);
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~ARMv5();
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void Reset() override;
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void DoSavestate(Savestate* file) override;
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void UpdateRegionTimings(u32 addrstart, u32 addrend);
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void FillPipeline() override;
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void JumpTo(u32 addr, bool restorecpsr = false) override;
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void PrefetchAbort();
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void DataAbort();
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template <CPUExecuteMode mode>
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void Execute();
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// all code accesses are forced nonseq 32bit
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u32 CodeRead32(u32 addr, bool branch);
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void DataRead8(u32 addr, u32* val) override;
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void DataRead16(u32 addr, u32* val) override;
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void DataRead32(u32 addr, u32* val) override;
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void DataRead32S(u32 addr, u32* val) override;
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void DataWrite8(u32 addr, u8 val) override;
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void DataWrite16(u32 addr, u16 val) override;
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void DataWrite32(u32 addr, u32 val) override;
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void DataWrite32S(u32 addr, u32 val) override;
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void AddCycles_C() override
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{
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// code only. always nonseq 32-bit for ARM9.
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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Cycles += numC;
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}
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void AddCycles_CI(s32 numI) override
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{
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// code+internal
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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Cycles += numC + numI;
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}
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void AddCycles_CDI() override
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{
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// LDR/LDM cycles. ARM9 seems to skip the internal cycle there.
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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s32 numD = DataCycles;
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//if (DataRegion != CodeRegion)
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Cycles += std::max(numC + numD - 6, std::max(numC, numD));
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//else
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// Cycles += numC + numD;
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}
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void AddCycles_CD() override
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{
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// TODO: ITCM data fetches shouldn't be parallelized, they say
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s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
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s32 numD = DataCycles;
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//if (DataRegion != CodeRegion)
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Cycles += std::max(numC + numD - 6, std::max(numC, numD));
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//else
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// Cycles += numC + numD;
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}
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void GetCodeMemRegion(u32 addr, MemRegion* region);
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void CP15Reset();
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void CP15DoSavestate(Savestate* file);
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void UpdateDTCMSetting();
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void UpdateITCMSetting();
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void UpdatePURegion(u32 n);
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void UpdatePURegions(bool update_all);
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u32 RandomLineIndex();
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void ICacheLookup(u32 addr);
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void ICacheInvalidateByAddr(u32 addr);
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void ICacheInvalidateAll();
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void CP15Write(u32 id, u32 val);
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u32 CP15Read(u32 id) const;
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u32 CP15Control;
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u32 RNGSeed;
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u32 DTCMSetting, ITCMSetting;
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// for aarch64 JIT they need to go up here
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// to be addressable by a 12-bit immediate
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u32 ITCMSize;
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u32 DTCMBase, DTCMMask;
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s32 RegionCodeCycles;
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u8 ITCM[ITCMPhysicalSize];
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u8* DTCM;
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u8 ICache[0x2000];
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u32 ICacheTags[64*4];
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u8 ICacheCount[64];
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u32 PU_CodeCacheable;
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u32 PU_DataCacheable;
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u32 PU_DataCacheWrite;
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u32 PU_CodeRW;
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u32 PU_DataRW;
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u32 PU_Region[8];
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// 0=dataR 1=dataW 2=codeR 4=datacache 5=datawrite 6=codecache
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u8 PU_PrivMap[0x100000];
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u8 PU_UserMap[0x100000];
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// games operate under system mode, generally
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//#define PU_Map PU_PrivMap
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u8* PU_Map;
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// code/16N/32N/32S
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u8 MemTimings[0x100000][4];
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u8* CurICacheLine;
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bool (*GetMemRegion)(u32 addr, bool write, MemRegion* region);
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#ifdef GDBSTUB_ENABLED
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u32 ReadMem(u32 addr, int size) override;
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void WriteMem(u32 addr, int size, u32 v) override;
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#endif
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protected:
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u8 BusRead8(u32 addr) override;
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u16 BusRead16(u32 addr) override;
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u32 BusRead32(u32 addr) override;
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void BusWrite8(u32 addr, u8 val) override;
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void BusWrite16(u32 addr, u16 val) override;
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void BusWrite32(u32 addr, u32 val) override;
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};
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class ARMv4 : public ARM
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{
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public:
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ARMv4(melonDS::NDS& nds, std::optional<GDBArgs> gdb, bool jit);
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void FillPipeline() override;
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void JumpTo(u32 addr, bool restorecpsr = false) override;
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template <CPUExecuteMode mode>
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void Execute();
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u16 CodeRead16(u32 addr)
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{
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return BusRead16(addr);
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}
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u32 CodeRead32(u32 addr)
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{
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return BusRead32(addr);
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}
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void DataRead8(u32 addr, u32* val) override;
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void DataRead16(u32 addr, u32* val) override;
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void DataRead32(u32 addr, u32* val) override;
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void DataRead32S(u32 addr, u32* val) override;
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void DataWrite8(u32 addr, u8 val) override;
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void DataWrite16(u32 addr, u16 val) override;
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void DataWrite32(u32 addr, u32 val) override;
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void DataWrite32S(u32 addr, u32 val) override;
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void AddCycles_C() override;
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void AddCycles_CI(s32 num) override;
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void AddCycles_CDI() override;
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void AddCycles_CD() override;
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protected:
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u8 BusRead8(u32 addr) override;
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u16 BusRead16(u32 addr) override;
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u32 BusRead32(u32 addr) override;
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void BusWrite8(u32 addr, u8 val) override;
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void BusWrite16(u32 addr, u16 val) override;
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void BusWrite32(u32 addr, u32 val) override;
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};
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namespace ARMInterpreter
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{
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void A_UNK(ARM* cpu);
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void T_UNK(ARM* cpu);
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}
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}
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#endif // ARM_H
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