mirror of
https://github.com/melonDS-emu/melonDS.git
synced 2024-11-14 13:27:41 -07:00
594286ee5d
* fix dumb bug of the year: ARM LDR opcodes would accidentally read twice, which fucked with things like the IPC FIFO.
235 lines
5.0 KiB
C++
235 lines
5.0 KiB
C++
/*
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Copyright 2016-2017 StapleButter
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#ifndef ARM_H
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#define ARM_H
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#include "types.h"
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#include "NDS.h"
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#include "CP15.h"
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// lame
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#define C_S(x) x
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#define C_N(x) x
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#define C_I(x) x
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#define ROR(x, n) (((x) >> (n)) | ((x) << (32-(n))))
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class ARM
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{
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public:
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ARM(u32 num);
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~ARM(); // destroy shit
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void Reset();
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void JumpTo(u32 addr, bool restorecpsr = false);
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void RestoreCPSR();
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void Halt(u32 halt)
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{
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Halted = halt;
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}
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s32 Execute();
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bool CheckCondition(u32 code)
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{
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if (code == 0xE) return true;
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if (ConditionTable[code] & (1 << (CPSR>>28))) return true;
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return false;
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}
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void SetC(bool c)
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{
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if (c) CPSR |= 0x20000000;
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else CPSR &= ~0x20000000;
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}
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void SetNZ(bool n, bool z)
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{
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CPSR &= ~0xC0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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}
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void SetNZCV(bool n, bool z, bool c, bool v)
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{
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CPSR &= ~0xF0000000;
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if (n) CPSR |= 0x80000000;
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if (z) CPSR |= 0x40000000;
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if (c) CPSR |= 0x20000000;
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if (v) CPSR |= 0x10000000;
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}
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void UpdateMode(u32 oldmode, u32 newmode);
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void TriggerIRQ();
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u16 CodeRead16(u32 addr)
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{
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u16 val;
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// TODO eventually: on ARM9, THUMB opcodes are prefetched with 32bit reads
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if (!Num)
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{
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if (!CP15::HandleCodeRead16(addr, &val))
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val = NDS::ARM9Read16(addr);
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}
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else
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val = NDS::ARM7Read16(addr);
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Cycles += Waitstates[0][(addr>>24)&0xF];
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return val;
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}
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u32 CodeRead32(u32 addr)
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{
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u32 val;
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if (!Num)
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{
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if (!CP15::HandleCodeRead32(addr, &val))
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val = NDS::ARM9Read32(addr);
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}
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else
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val = NDS::ARM7Read32(addr);
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Cycles += Waitstates[1][(addr>>24)&0xF];
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return val;
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}
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u8 DataRead8(u32 addr, u32 forceuser=0)
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{
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u8 val;
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if (!Num)
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{
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if (!CP15::HandleDataRead8(addr, &val, forceuser))
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val = NDS::ARM9Read8(addr);
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}
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else
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val = NDS::ARM7Read8(addr);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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return val;
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}
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u16 DataRead16(u32 addr, u32 forceuser=0)
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{
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u16 val;
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addr &= ~1;
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if (!Num)
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{
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if (!CP15::HandleDataRead16(addr, &val, forceuser))
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val = NDS::ARM9Read16(addr);
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}
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else
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val = NDS::ARM7Read16(addr);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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return val;
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}
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u32 DataRead32(u32 addr, u32 forceuser=0)
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{
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u32 val;
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addr &= ~3;
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if (!Num)
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{
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if (!CP15::HandleDataRead32(addr, &val, forceuser))
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val = NDS::ARM9Read32(addr);
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}
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else
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val = NDS::ARM7Read32(addr);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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return val;
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}
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void DataWrite8(u32 addr, u8 val, u32 forceuser=0)
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{
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if (!Num)
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{
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if (!CP15::HandleDataWrite8(addr, val, forceuser))
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NDS::ARM9Write8(addr, val);
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}
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else
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NDS::ARM7Write8(addr, val);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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}
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void DataWrite16(u32 addr, u16 val, u32 forceuser=0)
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{
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addr &= ~1;
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if (!Num)
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{
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if (!CP15::HandleDataWrite16(addr, val, forceuser))
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NDS::ARM9Write16(addr, val);
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}
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else
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NDS::ARM7Write16(addr, val);
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Cycles += Waitstates[2][(addr>>24)&0xF];
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}
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void DataWrite32(u32 addr, u32 val, u32 forceuser=0)
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{
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addr &= ~3;
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if (!Num)
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{
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if (!CP15::HandleDataWrite32(addr, val, forceuser))
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NDS::ARM9Write32(addr, val);
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}
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else
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NDS::ARM7Write32(addr, val);
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Cycles += Waitstates[3][(addr>>24)&0xF];
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}
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u32 Num;
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// waitstates:
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// 0=code16 1=code32 2=data16 3=data32
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// TODO eventually: nonsequential waitstates
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s32 Waitstates[4][16];
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s32 Cycles;
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s32 CyclesToRun;
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u32 Halted;
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u32 R[16]; // heh
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u32 CPSR;
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u32 R_FIQ[8]; // holding SPSR too
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u32 R_SVC[3];
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u32 R_ABT[3];
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u32 R_IRQ[3];
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u32 R_UND[3];
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u32 CurInstr;
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u32 NextInstr[2];
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u32 ExceptionBase;
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static u32 ConditionTable[16];
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u32 debug;
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};
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#endif // ARM_H
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