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Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

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* Add host CPU memory barriers for DMB/DSB and ordered load/store

* PPTC version bump

* Revert to old barrier order
This commit is contained in:
gdkchan
2022-01-21 12:47:34 -03:00
committed by GitHub
parent 7e967d796c
commit f0824fde9f
6 changed files with 21 additions and 5 deletions
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ARMeilleure/IntermediateRepresentation/Instruction.cs
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@ -26,6 +26,7 @@ namespace ARMeilleure.IntermediateRepresentation
Load16,
Load8,
LoadArgument,
MemoryBarrier,
Multiply,
Multiply64HighSI,
Multiply64HighUI,