Commit Graph

85 Commits

Author SHA1 Message Date
745200373b gdb: Remove unused using 2025-06-21 01:24:06 +08:00
4a8463c2f7 Add GDB Stub
Author: merry, svc64
2025-06-20 16:17:28 +08:00
77a797f154 Revert "Structural and Memory Safety Improvements, Analyzer Cleanup (ryubing/ryujinx!47)"
This reverts merge request !47
2025-06-15 20:45:26 -05:00
ea027d65a7 Structural and Memory Safety Improvements, Analyzer Cleanup (ryubing/ryujinx!47)
See merge request ryubing/ryujinx!47
2025-06-11 17:58:27 -05:00
053a9cb549 fix: use accurate length for enumerating
See merge request ryubing/ryujinx!49
2025-06-03 23:20:55 -05:00
361d0c5632 Fix ~3500 analyser issues
See merge request ryubing/ryujinx!44
2025-05-30 17:08:34 -05:00
84686d50cd Revert "PPTC: fix rare EndOfStreamException in ContainsBlacklistedFunctions"
This reverts commit 1156307ef9
2025-05-29 02:37:52 -05:00
9233fe86b0 [ci skip] infra: After a quick test, ARMeilleure didn't even use anything from Ryujinx.Common. 2025-05-28 23:52:06 -05:00
1156307ef9 PPTC: fix rare EndOfStreamException in ContainsBlacklistedFunctions 2025-05-28 23:35:52 -05:00
11cc80f7fc infra: Generate .nupkg when building ARMeilleure, Ryujinx.Common, and Ryujinx.Memory.
Additionally added a script to push them to Ryubing GitLab package registry. This script is my use only since it assumes you have the necessary authentication locally & on the server.

TODO: figure out a way to get proper versioning for them.
2025-05-18 03:10:38 -05:00
9b429afbb4 fix: PPTC blacklist trigger conditions
See merge request ryubing/ryujinx!28
2025-04-27 16:57:57 -05:00
c4ea0e0df2 Reset PPTC Carriers on invalidation
See merge request ryubing/ryujinx!26
2025-04-24 12:48:22 -05:00
4c9e8f8e5c reset infoStreams when the cache is invalid
See merge request ryubing/ryujinx!23
2025-04-22 21:42:41 -05:00
a3596ba858 Reset in-memory JIT cache on game quit + fix Purge PPTC (#709)
Jit cache now fully resets when booting a game multiple times.
This should fix random jit cache crashes.
Also removed some redundant code related to region allocation and fixed
PPTC Purge not fully purging all PPTC files in the backup folder.
2025-02-25 15:34:21 -06:00
c1002d4826 misc: chore: collection expressions & target typed new in ARMeilleure & Ryujinx.Cpu 2025-02-18 21:34:09 -06:00
855161b23b Prevent log from showing negative JIT cache sizes (32bit-int overflow) (#664)
![image](https://github.com/user-attachments/assets/5820ce7b-cbfe-4908-8f5e-7ee82040ee1a)
2025-02-14 21:37:19 -06:00
6ab899f621 misc: chore: [ci skip] Use explicit types & target-typed new 2025-02-10 16:44:26 -06:00
faacec9801 JIT Cache Regions + HLE SoNoSigpipe BSD socket mapping (#615)
Instead of one big 2048MB JIT Cache that'd crash the emulator when maxed
out, we now have it where we add 256MB JIT Cache regions when needed,
helping reduce allocated memory where games don't use the JIT cache for
it, and helping bigger games that DO need JIT cache bigger than 2048MB!

![image](https://github.com/user-attachments/assets/ff17dc48-6028-4377-8c73-746ab21ab83b)
(SSBU goes past the 2048MB JIT Cache limit that would normally crash
Ryujinx ^)

Also I added a BSD socket that Baba is You's networking for downloading
custom levels uses.
2025-02-10 15:53:44 -06:00
ff05e03cc8 misc: chore: Remove unused using directives across entire solution. 2025-01-30 20:27:17 -06:00
707c9ef748 misc: chore: slightly improve PTC init log line 2025-01-28 22:25:01 -06:00
7085bafa60 PPTC Profiles (#370)
Added functionality that allows ExeFS mods to compile to their own PPTC
Profile and therefore store PTC data between sessions.
The feature calculates the hash of the currently loaded ExeFS mods and
stores the PPTC data in a profile that matches said hash, so you can
have multiple ExeFS loadouts without causing issues. This includes
different versions of the same mod as their hashes will be different.
Using this PR should be seamless as the JIT Sparse PR already laid the
groundwork for PPTC Profiles and this PR just allows ExeFS mods to load
and store their own profiles besides the `default` profile.

 **WARNING!** 
**This will update your PPTC profile version, which means the
PPTC profile will be invalidated if you try to run a PR/Build/Branch
that does not include this change!**
**This is only relevant for the default PPTC Profile, as any other profiles do not exist to older versions!**
2025-01-28 20:36:58 -06:00
9cb3b40ffc misc: chore: Use collection expressions in ARMeilleure 2025-01-26 15:31:44 -06:00
15d1528774 misc: chore: Fix object creation in ARMeilleure 2025-01-26 15:17:12 -06:00
e0567c5ce9 misc: chore: Use explicit types in ARMeilleure project 2025-01-25 14:01:13 -06:00
850df38f1e cleaup imports 2025-01-04 06:54:46 -06:00
c8d598d5ac use UnmanagedCallersOnly for delegates 2025-01-04 06:52:25 -06:00
17233d30da misc: give various threads dedicated names
Move all title ID lists into a TitleIDs class in Ryujinx.Common, with helpers.
Unify & simplify Auto graphics backend selection logic
2024-12-26 00:29:00 -06:00
ff6628149d Migrate to .NET 9 (#198) 2024-12-19 18:52:25 -06:00
17483aad24 ARMeilleure: Allow TPIDR2_EL0 to be set properly (#339) 2024-12-02 14:42:07 -06:00
facc12a94a JIT Sparse Function Table random crash fix (#319)
A couple of games have random crashing with the JIT Sparse Ftable changes, and it seems to have been caused by an insufficient int size returned by `AddressTableLevel#GetValue(ulong address)`.
It was 32 bits (Int32), but the GiantBlock (which is the current address table impl) uses potentially 36 bits for the first level.
2024-11-29 16:32:55 -06:00
baf179efdb ignore macos attribute files (#302) 2024-11-28 16:55:51 -06:00
e653848a2c JIT Sparse Function Table (#250)
More up to date build of the JIT Sparse PR for continued development.
JIT Sparse Function Table was originally developed by riperiperi for the
original Ryujinx project, and decreased the amount of layers in the
Function Table structure, to decrease lookup times at the cost of
slightly higher RAM usage.
This PR rebalances the JIT Sparse Function Table to be a bit more RAM
intensive, but faster in workloads where the JIT Function Table is a
bottleneck. Faster RAM will see a bigger impact and slower RAM (DDR3 and
potentially slow DDR4) will see a slight performance decrease.
This PR also implements a base for a PPTC profile system that could
allow for PPTC with ExeFS mods enabled in the future.
This PR also potentially fixes a strange issue where Avalonia would time
out in some rare instances, e.g. when running ExeFS mods with TotK and a
strange controller configuration.

---------

Co-authored-by: Evan Husted <gr33m11@gmail.com>
2024-11-22 15:33:44 -06:00
c0a4d95c5d ARMeilleure: Implement TPIDR2_EL0 (#280)
This is an implementation of the TPIDR2_EL0 register. There may be more
potential use-cases for this register not included in this PR, but this
implements the use-case seen in SuperTuxKart.
2024-11-19 13:02:24 -06:00
4aae82bad1 misc: Small cleanups 2024-11-10 15:34:24 -06:00
6911e288bc misc: Code cleanups. 2024-11-01 12:00:07 -05:00
dfb4854d19 misc: Replace references to IntPtr/UIntPtr with nint/nuint + code cleanups. 2024-10-26 08:46:50 -05:00
235083ad75 misc: Code cleanups & improvements, again 2024-10-17 01:21:32 -05:00
0faf3f5709 CPU: Add low-power PPTC load mode.
Specifically, this setting causes the translation load core count to get reduced by two-thirds, for lower-power but still fast loading, and for unstable CPUs.
2024-10-14 21:48:21 -05:00
cb31d79164 misc: Collapse XXHash128 into Hash128. 2024-10-12 21:39:30 -05:00
62216782ca Make GetFunctionPointerForDelegate as explicit as possible (#7279)
Co-authored-by: gdk <gab.dark.100@gmail.com>
2024-09-15 17:39:10 -03:00
2f36a6665c Implement Arm32 VSHLL and QADD16 instructions (#7301) 2024-09-12 18:22:30 -03:00
3c61d560c3 Fix deadlock in background translation thread shutdown (#7239)
TryDequeue checks for _disposed before taking the lock.  If another
thread calls Dispose before it takes the lock, it won't get woken up by
the PulseAll call, and will deadlock in Monitor.Wait.

Double-checking _disposed with the lock taken should avoid this.
2024-08-27 19:10:24 +02:00
8d8983049e Implement UQADD16, UQADD8, UQSUB16, UQSUB8, VQRDMULH, VSLI and VSWP Arm32 instructions (#7174) 2024-08-08 17:07:24 -03:00
0afa8f2c14 JIT: Coalesce copies on LSRA with simple register preferencing (#6950)
* JIT: Coalesce copies on LSRA with simple register preferencing

* PPTC version bump
2024-06-19 09:39:29 -03:00
d25a084858 JIT: Ensure entry block has no predecessors on RegisterUsage pass (#6951) 2024-06-19 09:25:47 -03:00
888402ecaf Avoid inexact read with 'Stream.Read' (#6847) 2024-06-02 22:16:48 +02:00
a23d8cb92f Replace "List.ForEach" for "foreach" (#6783)
* Replace "List.ForEach" for "foreach"

* dotnet format

* Update Ptc.cs

* Update GpuContext.cs
2024-05-08 13:53:25 +02:00
543d75a587 CPU: Produce non-inf results for RSQRTE instruction with subnormal inputs (#6634)
* CPU: Produce non-inf results for RSQRTE instruction with subnormal inputs

* PPTC version bump
2024-04-09 14:34:14 -03:00
808803d97a CPU: Fix PC alignment for ADR thumb instruction (#6613)
* Fix PC alignment for ADR thumb instruction

* PPTC version bump
2024-04-07 18:17:49 -03:00
b323a01738 Implement host tracked memory manager mode (#6356)
* Add host tracked memory manager mode

* Skipping flush is no longer needed

* Formatting + revert unrelated change

* LightningJit: Ensure that dest register is saved for load ops that do partial updates

* avoid allocations when doing address space lookup

Add missing improvement

* IsRmwMemory -> IsPartialRegisterUpdateMemory

* Ensure we iterate all private allocations in range

* PR feedback and potential fixes

* Simplified bridges a lot

* Skip calling SignalMappingChanged if Guest is true

* Late map bridge too

* Force address masking for prefetch instructions

* Reprotection for bridges

* Move partition list validation to separate debug method

* Move host tracked related classes to HostTracked folder

* New HostTracked namespace

* Move host tracked modes to the end of enum to avoid PPTC invalidation

---------

Co-authored-by: riperiperi <rhy3756547@hotmail.com>
2024-03-26 23:33:24 -03:00