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DSPLLE: More accurately handle initialization behavior
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@ -379,6 +379,7 @@ void SDSP::DoState(PointerWrap& p)
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p.Do(r);
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p.Do(pc);
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p.Do(control_reg);
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p.Do(control_reg_init_code_clear_time);
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p.Do(reg_stack_ptrs);
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p.Do(exceptions);
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p.Do(external_interrupt_waiting);
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@ -424,6 +424,7 @@ struct SDSP
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// The engine has control over 0x0C07 of this reg.
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// Bits are defined in a struct in DSP.cpp.
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u16 control_reg = 0;
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u64 control_reg_init_code_clear_time = 0;
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u8 reg_stack_ptrs[4]{};
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u8 exceptions = 0; // pending exceptions
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@ -577,9 +578,6 @@ public:
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Interpreter::Interpreter& GetInterpreter() { return *m_dsp_interpreter; }
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const Interpreter::Interpreter& GetInterpreter() const { return *m_dsp_interpreter; }
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bool GetInitHax() const { return m_init_hax; }
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void SetInitHax(bool value) { m_init_hax = value; }
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private:
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SDSP m_dsp;
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DSPBreakpoints m_dsp_breakpoints;
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@ -39,13 +39,6 @@ u16 SDSP::ReadMailboxLow(Mailbox mailbox)
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const u32 value = GetMailbox(mailbox).load(std::memory_order_acquire);
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GetMailbox(mailbox).store(value & ~0x80000000, std::memory_order_release);
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if (m_dsp_core.GetInitHax() && mailbox == Mailbox::DSP)
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{
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m_dsp_core.SetInitHax(false);
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m_dsp_core.Reset();
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return 0x4348;
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* const type = mailbox == Mailbox::DSP ? "DSP" : "CPU";
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DEBUG_LOG_FMT(DSP_MAIL, "{}(RM) B:{} M:{:#010x} (pc={:#06x})", type, static_cast<int>(mailbox),
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@ -57,11 +50,6 @@ u16 SDSP::ReadMailboxLow(Mailbox mailbox)
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u16 SDSP::ReadMailboxHigh(Mailbox mailbox)
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{
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if (m_dsp_core.GetInitHax() && mailbox == Mailbox::DSP)
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{
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return 0x8054;
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}
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// TODO: mask away the top bit?
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return static_cast<u16>(PeekMailbox(mailbox) >> 16);
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}
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@ -7,12 +7,17 @@
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#include "Common/Assert.h"
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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#include "Common/MemoryUtil.h"
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#include "Core/CoreTiming.h"
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#include "Core/DSP/DSPAnalyzer.h"
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#include "Core/DSP/DSPCore.h"
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#include "Core/DSP/DSPHost.h"
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#include "Core/DSP/DSPTables.h"
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#include "Core/DSP/Interpreter/DSPIntCCUtil.h"
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#include "Core/DSP/Interpreter/DSPIntTables.h"
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#include "Core/HW/Memmap.h"
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#include "Core/HW/SystemTimers.h"
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namespace DSP::Interpreter
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{
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@ -214,6 +219,17 @@ int Interpreter::RunCycles(int cycles)
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// NOTE: These have nothing to do with SDSP::r::cr!
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void Interpreter::WriteControlRegister(u16 val)
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{
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auto& state = m_dsp_core.DSPState();
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if ((state.control_reg & CR_HALT) != (val & CR_HALT))
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{
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// This bit is handled by Interpreter::RunCycles and DSPEmitter::CompileDispatcher
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL halt bit changed: {:04x} -> {:04x}, PC {:04x}",
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state.control_reg, val, state.pc);
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}
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// The CR_EXTERNAL_INT bit is handled by DSPLLE::DSP_WriteControlRegister
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// reset
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if ((val & CR_RESET) != 0)
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{
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@ -221,33 +237,42 @@ void Interpreter::WriteControlRegister(u16 val)
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m_dsp_core.Reset();
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val &= ~CR_RESET;
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}
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// init
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else if (val == CR_HALT)
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// init - unclear if writing CR_INIT_CODE does something. Clearing CR_INIT immediately sets
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// CR_INIT_CODE, which gets unset a bit later...
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if (((state.control_reg & CR_INIT) != 0) && ((val & CR_INIT) == 0))
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{
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// HAX!
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// OSInitAudioSystem ucode should send this mail - not DSP core itself
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INFO_LOG_FMT(DSPLLE, "DSP_CONTROL INIT");
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m_dsp_core.SetInitHax(true);
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val |= CR_INIT;
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// Copy 1024(?) bytes of uCode from main memory 0x81000000 (or is it ARAM 00000000?)
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// to IMEM 0000 and jump to that code
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// TODO: Determine exactly how this initialization works
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state.pc = 0;
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Common::UnWriteProtectMemory(state.iram, DSP_IRAM_BYTE_SIZE, false);
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Host::DMAToDSP(state.iram, 0x81000000, 0x1000);
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Common::WriteProtectMemory(state.iram, DSP_IRAM_BYTE_SIZE, false);
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Host::CodeLoaded(m_dsp_core, 0x81000000, 0x1000);
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val &= ~CR_INIT;
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val |= CR_INIT_CODE;
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// Number obtained from real hardware on a Wii, but it's not perfectly consistent
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state.control_reg_init_code_clear_time = SystemTimers::GetFakeTimeBase() + 130;
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}
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// update cr
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m_dsp_core.DSPState().control_reg = val;
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state.control_reg = val;
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}
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u16 Interpreter::ReadControlRegister()
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{
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auto& state = m_dsp_core.DSPState();
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if ((state.pc & 0x8000) != 0)
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if ((state.control_reg & CR_INIT_CODE) != 0)
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{
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state.control_reg |= CR_INIT;
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if (SystemTimers::GetFakeTimeBase() >= state.control_reg_init_code_clear_time)
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state.control_reg &= ~CR_INIT_CODE;
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else
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CoreTiming::ForceExceptionCheck(50); // Keep checking
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}
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else
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{
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state.control_reg &= ~CR_INIT;
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}
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return state.control_reg;
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}
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@ -330,6 +330,7 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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s_dspState.DSPReset = tmpControl.DSPReset;
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s_dspState.DSPAssertInt = tmpControl.DSPAssertInt;
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s_dspState.DSPHalt = tmpControl.DSPHalt;
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s_dspState.DSPInitCode = tmpControl.DSPInitCode;
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s_dspState.DSPInit = tmpControl.DSPInit;
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// Interrupt (mask)
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@ -346,7 +347,6 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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s_dspState.DSP = 0;
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// unknown
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s_dspState.DSPInitCode = tmpControl.DSPInitCode;
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s_dspState.pad = tmpControl.pad;
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if (s_dspState.pad != 0)
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{
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@ -74,7 +74,7 @@ static std::recursive_mutex g_save_thread_mutex;
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static std::thread g_save_thread;
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// Don't forget to increase this after doing changes on the savestate system
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constexpr u32 STATE_VERSION = 141; // Last changed in PR 8067
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constexpr u32 STATE_VERSION = 142; // Last changed in PR 10732
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// Maps savestate versions to Dolphin versions.
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// Versions after 42 don't need to be added to this list,
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