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JitArm64: Merge ps_mergeXX.
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1b6d9dfc4e
commit
09af32c063
@ -151,10 +151,7 @@ public:
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void ps_abs(UGeckoInstruction inst);
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void ps_madd(UGeckoInstruction inst);
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void ps_maddsX(UGeckoInstruction inst);
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void ps_merge00(UGeckoInstruction inst);
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void ps_merge01(UGeckoInstruction inst);
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void ps_merge10(UGeckoInstruction inst);
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void ps_merge11(UGeckoInstruction inst);
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void ps_mergeXX(UGeckoInstruction inst);
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void ps_mr(UGeckoInstruction inst);
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void ps_msub(UGeckoInstruction inst);
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void ps_muls0(UGeckoInstruction inst);
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@ -78,7 +78,7 @@ void JitArm64::ps_maddsX(UGeckoInstruction inst)
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fpr.Unlock(V0);
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}
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void JitArm64::ps_merge00(UGeckoInstruction inst)
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void JitArm64::ps_mergeXX(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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@ -90,65 +90,37 @@ void JitArm64::ps_merge00(UGeckoInstruction inst)
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ARM64Reg VB = fpr.R(b, REG_REG);
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ARM64Reg VD = fpr.RW(d, REG_REG);
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m_float_emit.TRN1(64, VD, VA, VB);
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}
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void JitArm64::ps_merge01(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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ARM64Reg VA = fpr.R(a, REG_REG);
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ARM64Reg VB = fpr.R(b, REG_REG);
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ARM64Reg VD = fpr.RW(d, REG_REG);
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m_float_emit.INS(64, VD, 0, VA, 0);
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m_float_emit.INS(64, VD, 1, VB, 1);
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}
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void JitArm64::ps_merge10(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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ARM64Reg VA = fpr.R(a, REG_REG);
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ARM64Reg VB = fpr.R(b, REG_REG);
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ARM64Reg VD = fpr.RW(d, REG_REG);
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if (d != a && d != b)
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switch (inst.SUBOP10)
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{
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m_float_emit.INS(64, VD, 0, VA, 1);
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m_float_emit.INS(64, VD, 1, VB, 0);
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case 528: //00
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m_float_emit.TRN1(64, VD, VA, VB);
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break;
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case 560: //01
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m_float_emit.INS(64, VD, 0, VA, 0);
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m_float_emit.INS(64, VD, 1, VB, 1);
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break;
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case 592: //10
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if (d != a && d != b)
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{
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m_float_emit.INS(64, VD, 0, VA, 1);
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m_float_emit.INS(64, VD, 1, VB, 0);
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}
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else
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{
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.INS(64, V0, 0, VA, 1);
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m_float_emit.INS(64, V0, 1, VB, 0);
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m_float_emit.ORR(VD, V0, V0);
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fpr.Unlock(V0);
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}
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break;
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case 624: //11
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m_float_emit.TRN2(64, VD, VA, VB);
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break;
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default:
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_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");
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break;
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}
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else
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{
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ARM64Reg V0 = fpr.GetReg();
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m_float_emit.INS(64, V0, 0, VA, 1);
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m_float_emit.INS(64, V0, 1, VB, 0);
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m_float_emit.ORR(VD, V0, V0);
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fpr.Unlock(V0);
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}
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}
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void JitArm64::ps_merge11(UGeckoInstruction inst)
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{
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INSTRUCTION_START
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JITDISABLE(bJITPairedOff);
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FALLBACK_IF(inst.Rc);
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u32 a = inst.FA, b = inst.FB, d = inst.FD;
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ARM64Reg VA = fpr.R(a, REG_REG);
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ARM64Reg VB = fpr.R(b, REG_REG);
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ARM64Reg VD = fpr.RW(d, REG_REG);
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m_float_emit.TRN2(64, VD, VA, VB);
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}
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void JitArm64::ps_mr(UGeckoInstruction inst)
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@ -110,10 +110,10 @@ static GekkoOPTemplate table4[] =
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{64, &JitArm64::FallBackToInterpreter}, // ps_cmpu1
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{72, &JitArm64::ps_mr}, // ps_mr
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{96, &JitArm64::FallBackToInterpreter}, // ps_cmpo1
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{528, &JitArm64::ps_merge00}, // ps_merge00
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{560, &JitArm64::ps_merge01}, // ps_merge01
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{592, &JitArm64::ps_merge10}, // ps_merge10
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{624, &JitArm64::ps_merge11}, // ps_merge11
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{528, &JitArm64::ps_mergeXX}, // ps_merge00
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{560, &JitArm64::ps_mergeXX}, // ps_merge01
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{592, &JitArm64::ps_mergeXX}, // ps_merge10
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{624, &JitArm64::ps_mergeXX}, // ps_merge11
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{1014, &JitArm64::FallBackToInterpreter}, // dcbz_l
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};
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