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Compactify generated UID generator assembly and generally cleanup code by storing tev stage hash values in a struct.

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This commit is contained in:
NeoBrainX 2013-06-22 20:41:32 +02:00
parent 88d1195f93
commit 16ada5fa3d
2 changed files with 45 additions and 97 deletions
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62
Source/Core/VideoCommon/Src/PixelShaderGen.cpp
View File

@ -706,13 +706,11 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
out.Write("// TEV stage %d\n", n);
uid_data.bHasIndStage |= bHasIndStage << n;
uid_data.tevorders_n_texcoord |= (u64)texcoord << (3 * n);
uid_data.stagehash[n].hasindstage = bHasIndStage;
uid_data.stagehash[n].tevorders_texcoord = texcoord;
if (bHasIndStage)
{
uid_data.tevind_n_bs |= bpmem.tevind[n].bs << (2*n);
uid_data.tevind_n_bt |= bpmem.tevind[n].bt << (2*n);
uid_data.tevind_n_fmt |= bpmem.tevind[n].fmt << (2*n);
uid_data.stagehash[n].tevind = bpmem.tevind[n].hex & 0x7FFFFF;
out.Write("// indirect op\n");
// perform the indirect op on the incoming regular coordinates using indtex%d as the offset coords
@ -727,12 +725,10 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
out.Write("float3 indtevcrd%d = indtex%d * %s;\n", n, bpmem.tevind[n].bt, tevIndFmtScale[bpmem.tevind[n].fmt]);
// bias
uid_data.Set_tevind_bias(n, bpmem.tevind[n].bias);
if (bpmem.tevind[n].bias != ITB_NONE )
out.Write("indtevcrd%d.%s += %s;\n", n, tevIndBiasField[bpmem.tevind[n].bias], tevIndBiasAdd[bpmem.tevind[n].fmt]);
// multiply by offset matrix and scale
uid_data.Set_tevind_mid(n, bpmem.tevind[n].mid);
if (bpmem.tevind[n].mid != 0)
{
if (bpmem.tevind[n].mid <= 3)
@ -769,9 +765,6 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
// ---------
// Wrapping
// ---------
uid_data.Set_tevind_sw(n, bpmem.tevind[n].sw);
uid_data.Set_tevind_tw(n, bpmem.tevind[n].tw);
uid_data.tevind_n_fb_addprev |= bpmem.tevind[n].fb_addprev << n;
// wrap S
if (bpmem.tevind[n].sw == ITW_OFF)
@ -798,26 +791,8 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
TevStageCombiner::ColorCombiner &cc = bpmem.combiners[n].colorC;
TevStageCombiner::AlphaCombiner &ac = bpmem.combiners[n].alphaC;
uid_data.cc_n_d |= (u64)cc.d << (4*n);
uid_data.cc_n_c |= (u64)cc.c << (4*n);
uid_data.cc_n_b |= (u64)cc.b << (4*n);
uid_data.cc_n_a |= (u64)cc.a << (4*n);
uid_data.cc_n_bias |= cc.bias << (2*n);
uid_data.cc_n_op |= cc.op << n;
uid_data.cc_n_clamp |= cc.clamp << n;
uid_data.cc_n_shift |= cc.shift << (2*n);
uid_data.cc_n_dest |= cc.dest << (2*n);
uid_data.ac_n_rswap |= ac.rswap << (2*n);
uid_data.ac_n_tswap |= ac.tswap << (2*n);
uid_data.ac_n_d |= (u64)ac.d << (3*n);
uid_data.ac_n_c |= (u64)ac.c << (3*n);
uid_data.ac_n_b |= (u64)ac.b << (3*n);
uid_data.ac_n_a |= (u64)ac.a << (3*n);
uid_data.ac_n_bias |= ac.bias << (2*n);
uid_data.ac_n_op |= ac.op << n;
uid_data.ac_n_clamp |= ac.clamp << n;
uid_data.ac_n_shift |= ac.shift << (2*n);
uid_data.ac_n_dest |= ac.dest << (2*n);
uid_data.stagehash[n].cc = cc.hex & 0xFFFFFF;
uid_data.stagehash[n].ac = ac.hex & 0xFFFFF0; // Storing rswap and tswap later
if(cc.a == TEVCOLORARG_RASA || cc.a == TEVCOLORARG_RASC
|| cc.b == TEVCOLORARG_RASA || cc.b == TEVCOLORARG_RASC
@ -827,17 +802,19 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
|| ac.c == TEVALPHAARG_RASA || ac.d == TEVALPHAARG_RASA)
{
const int i = bpmem.combiners[n].alphaC.rswap;
uid_data.tevksel_n_swap1 |= bpmem.tevksel[i*2 ].swap1 << (2 * (i*2 ));
uid_data.tevksel_n_swap1 |= bpmem.tevksel[i*2+1].swap1 << (2 * (i*2+1));
uid_data.tevksel_n_swap2 |= bpmem.tevksel[i*2 ].swap2 << (2 * (i*2 ));
uid_data.tevksel_n_swap2 |= bpmem.tevksel[i*2+1].swap2 << (2 * (i*2+1));
uid_data.stagehash[n].ac |= bpmem.combiners[n].alphaC.rswap;
uid_data.stagehash[n].tevksel_swap1a = bpmem.tevksel[i*2].swap1;
uid_data.stagehash[n].tevksel_swap2a = bpmem.tevksel[i*2].swap2;
uid_data.stagehash[n].tevksel_swap1b = bpmem.tevksel[i*2+1].swap1;
uid_data.stagehash[n].tevksel_swap2b = bpmem.tevksel[i*2+1].swap2;
uid_data.stagehash[n].tevorders_colorchan = bpmem.tevorders[n / 2].getColorChan(n & 1);
char *rasswap = swapModeTable[bpmem.combiners[n].alphaC.rswap];
out.Write("rastemp = %s.%s;\n", tevRasTable[bpmem.tevorders[n / 2].getColorChan(n & 1)], rasswap);
out.Write("crastemp = frac(rastemp * (255.0f/256.0f)) * (256.0f/255.0f);\n");
}
uid_data.stagehash[n].tevorders_enable = bpmem.tevorders[n / 2].getEnable(n & 1);
if (bpmem.tevorders[n/2].getEnable(n&1))
{
if (!bHasIndStage)
@ -850,10 +827,13 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
}
const int i = bpmem.combiners[n].alphaC.tswap;
uid_data.tevksel_n_swap1 |= bpmem.tevksel[i*2 ].swap1 << (2 * (i*2 ));
uid_data.tevksel_n_swap1 |= bpmem.tevksel[i*2+1].swap1 << (2 * (i*2+1));
uid_data.tevksel_n_swap2 |= bpmem.tevksel[i*2 ].swap2 << (2 * (i*2 ));
uid_data.tevksel_n_swap2 |= bpmem.tevksel[i*2+1].swap2 << (2 * (i*2+1));
uid_data.stagehash[n].ac |= bpmem.combiners[n].alphaC.tswap << 2;
uid_data.stagehash[n].tevksel_swap1c = bpmem.tevksel[i*2].swap1;
uid_data.stagehash[n].tevksel_swap2c = bpmem.tevksel[i*2].swap2;
uid_data.stagehash[n].tevksel_swap1d = bpmem.tevksel[i*2+1].swap1;
uid_data.stagehash[n].tevksel_swap2d = bpmem.tevksel[i*2+1].swap2;
uid_data.stagehash[n].tevorders_texmap= bpmem.tevorders[n/2].getTexMap(n&1);
char *texswap = swapModeTable[bpmem.combiners[n].alphaC.tswap];
int texmap = bpmem.tevorders[n/2].getTexMap(n&1);
@ -871,8 +851,8 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
{
int kc = bpmem.tevksel[n / 2].getKC(n & 1);
int ka = bpmem.tevksel[n / 2].getKA(n & 1);
uid_data.set_tevksel_kcsel(n/2, n & 1, kc);
uid_data.set_tevksel_kasel(n/2, n & 1, ka);
uid_data.stagehash[n].tevksel_kc = kc;
uid_data.stagehash[n].tevksel_ka = ka;
out.Write("konsttemp = float4(%s, %s);\n", tevKSelTableC[kc], tevKSelTableA[ka]);
if(kc > 7 || ka > 7)
{

80
Source/Core/VideoCommon/Src/PixelShaderGen.h
View File

@ -96,69 +96,38 @@ struct pixel_shader_uid_data
else if (index == 3) { tevindref_bi4 = texmap; }
}
u64 tevorders_n_texcoord : 48; // 16 x 3 bits
struct {
u32 cc : 24;
u32 ac : 24;
u64 tevind_n_sw : 48; // 16 x 3 bits
u64 tevind_n_tw : 48; // 16 x 3 bits
u32 tevind_n_fb_addprev : 16; // 16 x 1 bit
u32 tevind_n_bs : 32; // 16 x 2 bits
u32 tevind_n_fmt : 32; // 16 x 2 bits
u32 tevind_n_bt : 32; // 16 x 2 bits
u64 tevind_n_bias : 48; // 16 x 3 bits
u64 tevind_n_mid : 64; // 16 x 4 bits
u32 tevorders_texmap : 3;
u32 tevorders_texcoord : 3;
u32 tevorders_enable : 1;
u32 tevorders_colorchan : 3;
u32 pad1 : 6;
// NOTE: These assume that the affected bits are zero before calling
void Set_tevind_sw(int index, u64 val)
{
tevind_n_sw |= val << (3*index);
}
void Set_tevind_tw(int index, u64 val)
{
tevind_n_tw |= val << (3*index);
}
void Set_tevind_bias(int index, u64 val)
{
tevind_n_bias |= val << (3*index);
}
void Set_tevind_mid(int index, u64 val)
{
tevind_n_mid |= val << (4*index);
}
u32 hasindstage : 1;
u32 tevind : 21;
u32 tevksel_swap1a : 2; // TODO: Doesn't fit here..
u32 tevksel_swap2a : 2; // TODO: Doesn't fit here..
u32 tevksel_swap1b : 2; // TODO: Doesn't fit here..
u32 tevksel_swap2b : 2; // TODO: Doesn't fit here..
u32 pad2 : 2;
u32 tevksel_n_swap1 : 16; // 8x2 bits
u32 tevksel_n_swap2 : 16; // 8x2 bits
u64 tevksel_n_kcsel0 : 40; // 8x5 bits
u64 tevksel_n_kasel0 : 40; // 8x5 bits
u64 tevksel_n_kcsel1 : 40; // 8x5 bits
u64 tevksel_n_kasel1 : 40; // 8x5 bits
void set_tevksel_kcsel(int index, int i, u64 value) { if (i) tevksel_n_kcsel1 |= value << (5*index); else tevksel_n_kcsel0 |= value << (5*index); }
void set_tevksel_kasel(int index, int i, u64 value) { if( i) tevksel_n_kasel1 |= value << (5*index); else tevksel_n_kasel0 |= value << (5*index); }
u32 tevksel_swap1c : 2; // TODO: Doesn't fit here..
u32 tevksel_swap2c : 2; // TODO: Doesn't fit here..
u32 tevksel_swap1d : 2; // TODO: Doesn't fit here..
u32 tevksel_swap2d : 2; // TODO: Doesn't fit here..
u32 tevksel_kc : 5;
u32 tevksel_ka : 5;
u32 pad3 : 14;
} stagehash[16];
u64 cc_n_d : 64; // 16x4 bits
u64 cc_n_c : 64; // 16x4 bits
u64 cc_n_b : 64; // 16x4 bits
u64 cc_n_a : 64; // 16x4 bits
u32 cc_n_bias : 32; // 16x2 bits
u32 cc_n_op : 16; // 16x1 bit
u32 cc_n_clamp : 16; // 16x1 bit
u32 cc_n_shift : 32; // 16x2 bits
u32 cc_n_dest : 32; // 16x2 bits
u32 ac_n_rswap : 32; // 16x2 bits
u32 ac_n_tswap : 32; // 16x2 bits
u64 ac_n_d : 48; // 16x3 bits
u64 ac_n_c : 48; // 16x3 bits
u64 ac_n_b : 48; // 16x3 bits
u64 ac_n_a : 48; // 16x3 bits
u32 ac_n_bias : 32; // 16x2 bits
u32 ac_n_op : 16; // 16x1 bit
u32 ac_n_clamp : 16; // 16x1 bit
u32 ac_n_shift : 32; // 16x2 bits
u32 ac_n_dest : 32; // 16x2 bits
u32 alpha_test_comp0 : 3;
u32 alpha_test_comp1 : 3;
u32 alpha_test_logic : 2;
u32 alpha_test_use_zcomploc_hack : 1;
u32 fog_proj : 1;
@ -169,7 +138,6 @@ struct pixel_shader_uid_data
u32 fast_depth_calc : 1;
u32 per_pixel_depth : 1;
u32 bHasIndStage : 16;
u32 xfregs_numTexGen_numTexGens : 4;