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Fix DSP loop test init order, add DSP pcm test

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xperia64
2022-06-20 18:16:11 -04:00
committed by Tillmann Karras
parent cd77e682ca
commit 21d5e3182d
2 changed files with 86 additions and 6 deletions
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13
Source/DSPSpy/tests/accelerator_loop_test.ds
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@ -9,12 +9,6 @@ lri $AC0.L, #0x0000 ; start
lri $AC1.M, #0x0000 ; end
lri $AC1.L, #0x0011 ; end
; Reset some registers
lri $AC0.H, #0xffff
sr @0xffda, $AC0.H ; pred scale
sr @0xffdb, $AC0.H ; yn1
sr @0xffdc, $AC0.H ; yn2
; Set the sample format
lri $AC0.H, #0x0
sr @0xffd1, $AC0.H
@ -27,6 +21,12 @@ srs @ACCAL, $AC0.L
srs @ACEAH, $AC1.M
srs @ACEAL, $AC1.L
; Reset some registers (these must be reset after setting FORMAT)
lri $AC0.H, #0xffff
sr @0xffda, $AC0.H ; pred scale
sr @0xffdb, $AC0.H ; yn1
sr @0xffdc, $AC0.H ; yn2
call load_hw_reg_to_regs
call send_back ; check the accelerator regs before a read
@ -34,6 +34,7 @@ bloopi #40, end_of_loop
lr $IX3, @ACDSAMP
call load_hw_reg_to_regs
call send_back ; after a read
nop ; Loops that end at a return of a call are buggy on hw
end_of_loop:
nop