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Merge pull request #9866 from JosJuice/jitarm64-hardcoded-exceptions
JitArm64: Don't hardcode exception constants
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commit
21d75099fc
@ -747,7 +747,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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// Inline exception check
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LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(Exceptions));
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TBZ(ARM64Reg::W30, 3, done_here); // EXCEPTION_EXTERNAL_INT
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TBZ(ARM64Reg::W30, IntLog2(EXCEPTION_EXTERNAL_INT), done_here);
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LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(msr));
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TBZ(ARM64Reg::W30, 11, done_here);
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MOVP2R(ARM64Reg::X30, &ProcessorInterface::m_InterruptCause);
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@ -773,7 +773,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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FixupBranch NoExtException = TBZ(WA, 3); // EXCEPTION_EXTERNAL_INT
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FixupBranch NoExtException = TBZ(WA, IntLog2(EXCEPTION_EXTERNAL_INT));
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FixupBranch Exception = B();
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SwitchToFarCode();
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const u8* done_here = GetCodePtr();
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@ -815,7 +815,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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fpr.Flush(FlushMode::MaintainState);
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, 26, 0); // EXCEPTION_FPU_UNAVAILABLE
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ORRI2R(WA, WA, EXCEPTION_FPU_UNAVAILABLE);
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STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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gpr.Unlock(WA);
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@ -24,7 +24,7 @@ void JitArm64::sc(UGeckoInstruction inst)
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ARM64Reg WA = gpr.GetReg();
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, 31, 0); // Same as WA | EXCEPTION_SYSCALL
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ORRI2R(WA, WA, EXCEPTION_SYSCALL);
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STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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gpr.Unlock(WA);
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@ -217,7 +217,7 @@ void JitArm64::twx(UGeckoInstruction inst)
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fpr.Flush(FlushMode::MaintainState);
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, 24, 0); // Same as WA | EXCEPTION_PROGRAM
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ORRI2R(WA, WA, EXCEPTION_PROGRAM);
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STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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gpr.Unlock(WA);
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