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Merge pull request #9866 from JosJuice/jitarm64-hardcoded-exceptions

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JitArm64: Don't hardcode exception constants
This commit is contained in:
Léo Lam
2021-07-06 15:21:38 +02:00
committed by GitHub
parent be0163b7ad 58698b8380
commit 21d75099fc
3 changed files with 5 additions and 5 deletions
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6
Source/Core/Core/PowerPC/JitArm64/Jit.cpp
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@ -747,7 +747,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
// Inline exception check // Inline exception check
LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(Exceptions));
TBZ(ARM64Reg::W30, 3, done_here); // EXCEPTION_EXTERNAL_INT TBZ(ARM64Reg::W30, IntLog2(EXCEPTION_EXTERNAL_INT), done_here);
LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(msr)); LDR(IndexType::Unsigned, ARM64Reg::W30, PPC_REG, PPCSTATE_OFF(msr));
TBZ(ARM64Reg::W30, 11, done_here); TBZ(ARM64Reg::W30, 11, done_here);
MOVP2R(ARM64Reg::X30, &ProcessorInterface::m_InterruptCause); MOVP2R(ARM64Reg::X30, &ProcessorInterface::m_InterruptCause);
@ -773,7 +773,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA); ARM64Reg XA = EncodeRegTo64(WA);
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
FixupBranch NoExtException = TBZ(WA, 3); // EXCEPTION_EXTERNAL_INT FixupBranch NoExtException = TBZ(WA, IntLog2(EXCEPTION_EXTERNAL_INT));
FixupBranch Exception = B(); FixupBranch Exception = B();
SwitchToFarCode(); SwitchToFarCode();
const u8* done_here = GetCodePtr(); const u8* done_here = GetCodePtr();
@ -815,7 +815,7 @@ void JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
fpr.Flush(FlushMode::MaintainState); fpr.Flush(FlushMode::MaintainState);
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, 26, 0); // EXCEPTION_FPU_UNAVAILABLE ORRI2R(WA, WA, EXCEPTION_FPU_UNAVAILABLE);
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
gpr.Unlock(WA); gpr.Unlock(WA);

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_Branch.cpp
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@ -24,7 +24,7 @@ void JitArm64::sc(UGeckoInstruction inst)
ARM64Reg WA = gpr.GetReg(); ARM64Reg WA = gpr.GetReg();
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, 31, 0); // Same as WA | EXCEPTION_SYSCALL ORRI2R(WA, WA, EXCEPTION_SYSCALL);
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
gpr.Unlock(WA); gpr.Unlock(WA);

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
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@ -217,7 +217,7 @@ void JitArm64::twx(UGeckoInstruction inst)
fpr.Flush(FlushMode::MaintainState); fpr.Flush(FlushMode::MaintainState);
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
ORR(WA, WA, 24, 0); // Same as WA | EXCEPTION_PROGRAM ORRI2R(WA, WA, EXCEPTION_PROGRAM);
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions)); STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
gpr.Unlock(WA); gpr.Unlock(WA);