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HW/ProcessorInterface: Rename member variables to fit naming convention.
This commit is contained in:
@ -89,7 +89,7 @@ void UpdateGatherPipe()
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size_t pipe_count = GetGatherPipeCount();
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size_t pipe_count = GetGatherPipeCount();
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size_t processed;
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size_t processed;
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u8* cur_mem = memory.GetPointer(processor_interface.Fifo_CPUWritePointer);
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u8* cur_mem = memory.GetPointer(processor_interface.m_fifo_cpu_write_pointer);
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for (processed = 0; pipe_count >= GATHER_PIPE_SIZE; processed += GATHER_PIPE_SIZE)
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for (processed = 0; pipe_count >= GATHER_PIPE_SIZE; processed += GATHER_PIPE_SIZE)
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{
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{
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// copy the GatherPipe
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// copy the GatherPipe
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@ -97,15 +97,15 @@ void UpdateGatherPipe()
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pipe_count -= GATHER_PIPE_SIZE;
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pipe_count -= GATHER_PIPE_SIZE;
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// increase the CPUWritePointer
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// increase the CPUWritePointer
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if (processor_interface.Fifo_CPUWritePointer == processor_interface.Fifo_CPUEnd)
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if (processor_interface.m_fifo_cpu_write_pointer == processor_interface.m_fifo_cpu_end)
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{
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{
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processor_interface.Fifo_CPUWritePointer = processor_interface.Fifo_CPUBase;
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processor_interface.m_fifo_cpu_write_pointer = processor_interface.m_fifo_cpu_base;
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cur_mem = memory.GetPointer(processor_interface.Fifo_CPUWritePointer);
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cur_mem = memory.GetPointer(processor_interface.m_fifo_cpu_write_pointer);
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}
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}
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else
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else
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{
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{
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cur_mem += GATHER_PIPE_SIZE;
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cur_mem += GATHER_PIPE_SIZE;
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processor_interface.Fifo_CPUWritePointer += GATHER_PIPE_SIZE;
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processor_interface.m_fifo_cpu_write_pointer += GATHER_PIPE_SIZE;
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}
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}
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system.GetCommandProcessor().GatherPipeBursted(system);
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system.GetCommandProcessor().GatherPipeBursted(system);
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@ -29,59 +29,60 @@ constexpr u32 FLIPPER_REV_C = 0x246500B1;
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void ProcessorInterfaceManager::DoState(PointerWrap& p)
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void ProcessorInterfaceManager::DoState(PointerWrap& p)
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{
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{
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p.Do(m_InterruptMask);
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p.Do(m_interrupt_mask);
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p.Do(m_InterruptCause);
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p.Do(m_interrupt_cause);
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p.Do(Fifo_CPUBase);
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p.Do(m_fifo_cpu_base);
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p.Do(Fifo_CPUEnd);
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p.Do(m_fifo_cpu_end);
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p.Do(Fifo_CPUWritePointer);
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p.Do(m_fifo_cpu_write_pointer);
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p.Do(m_ResetCode);
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p.Do(m_reset_code);
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}
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}
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void ProcessorInterfaceManager::Init()
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void ProcessorInterfaceManager::Init()
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{
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{
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m_InterruptMask = 0;
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m_interrupt_mask = 0;
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m_InterruptCause = 0;
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m_interrupt_cause = 0;
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Fifo_CPUBase = 0;
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m_fifo_cpu_base = 0;
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Fifo_CPUEnd = 0;
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m_fifo_cpu_end = 0;
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Fifo_CPUWritePointer = 0;
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m_fifo_cpu_write_pointer = 0;
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m_ResetCode = 0; // Cold reset
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m_reset_code = 0; // Cold reset
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m_InterruptCause = INT_CAUSE_RST_BUTTON | INT_CAUSE_VI;
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m_interrupt_cause = INT_CAUSE_RST_BUTTON | INT_CAUSE_VI;
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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auto& core_timing = system.GetCoreTiming();
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auto& core_timing = system.GetCoreTiming();
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toggleResetButton = core_timing.RegisterEvent("ToggleResetButton", ToggleResetButtonCallback);
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m_event_type_toggle_reset_button =
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iosNotifyResetButton =
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core_timing.RegisterEvent("ToggleResetButton", ToggleResetButtonCallback);
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m_event_type_ios_notify_reset_button =
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core_timing.RegisterEvent("IOSNotifyResetButton", IOSNotifyResetButtonCallback);
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core_timing.RegisterEvent("IOSNotifyResetButton", IOSNotifyResetButtonCallback);
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iosNotifyPowerButton =
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m_event_type_ios_notify_power_button =
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core_timing.RegisterEvent("IOSNotifyPowerButton", IOSNotifyPowerButtonCallback);
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core_timing.RegisterEvent("IOSNotifyPowerButton", IOSNotifyPowerButtonCallback);
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}
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}
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void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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{
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mmio->Register(base | PI_INTERRUPT_CAUSE, MMIO::DirectRead<u32>(&m_InterruptCause),
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mmio->Register(base | PI_INTERRUPT_CAUSE, MMIO::DirectRead<u32>(&m_interrupt_cause),
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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auto& processor_interface = system.GetProcessorInterface();
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auto& processor_interface = system.GetProcessorInterface();
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processor_interface.m_InterruptCause &= ~val;
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processor_interface.m_interrupt_cause &= ~val;
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processor_interface.UpdateException();
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processor_interface.UpdateException();
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}));
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}));
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mmio->Register(base | PI_INTERRUPT_MASK, MMIO::DirectRead<u32>(&m_InterruptMask),
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mmio->Register(base | PI_INTERRUPT_MASK, MMIO::DirectRead<u32>(&m_interrupt_mask),
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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auto& processor_interface = system.GetProcessorInterface();
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auto& processor_interface = system.GetProcessorInterface();
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processor_interface.m_InterruptMask = val;
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processor_interface.m_interrupt_mask = val;
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processor_interface.UpdateException();
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processor_interface.UpdateException();
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}));
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}));
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mmio->Register(base | PI_FIFO_BASE, MMIO::DirectRead<u32>(&Fifo_CPUBase),
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mmio->Register(base | PI_FIFO_BASE, MMIO::DirectRead<u32>(&m_fifo_cpu_base),
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MMIO::DirectWrite<u32>(&Fifo_CPUBase, 0xFFFFFFE0));
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MMIO::DirectWrite<u32>(&m_fifo_cpu_base, 0xFFFFFFE0));
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mmio->Register(base | PI_FIFO_END, MMIO::DirectRead<u32>(&Fifo_CPUEnd),
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mmio->Register(base | PI_FIFO_END, MMIO::DirectRead<u32>(&m_fifo_cpu_end),
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MMIO::DirectWrite<u32>(&Fifo_CPUEnd, 0xFFFFFFE0));
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MMIO::DirectWrite<u32>(&m_fifo_cpu_end, 0xFFFFFFE0));
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mmio->Register(base | PI_FIFO_WPTR, MMIO::DirectRead<u32>(&Fifo_CPUWritePointer),
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mmio->Register(base | PI_FIFO_WPTR, MMIO::DirectRead<u32>(&m_fifo_cpu_write_pointer),
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MMIO::DirectWrite<u32>(&Fifo_CPUWritePointer, 0xFFFFFFE0));
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MMIO::DirectWrite<u32>(&m_fifo_cpu_write_pointer, 0xFFFFFFE0));
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mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead<u32>(),
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mmio->Register(base | PI_FIFO_RESET, MMIO::InvalidRead<u32>(),
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MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
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MMIO::ComplexWrite<u32>([](Core::System&, u32, u32 val) {
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@ -109,15 +110,15 @@ void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](Core::System& system, u32) {
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mmio->Register(base | PI_RESET_CODE, MMIO::ComplexRead<u32>([](Core::System& system, u32) {
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auto& processor_interface = system.GetProcessorInterface();
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auto& processor_interface = system.GetProcessorInterface();
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Read PI_RESET_CODE: {:08x}",
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Read PI_RESET_CODE: {:08x}",
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processor_interface.m_ResetCode);
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processor_interface.m_reset_code);
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return processor_interface.m_ResetCode;
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return processor_interface.m_reset_code;
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}),
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}),
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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MMIO::ComplexWrite<u32>([](Core::System& system, u32, u32 val) {
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auto& processor_interface = system.GetProcessorInterface();
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auto& processor_interface = system.GetProcessorInterface();
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processor_interface.m_ResetCode = val;
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processor_interface.m_reset_code = val;
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INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_RESET_CODE: {:08x}",
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INFO_LOG_FMT(PROCESSORINTERFACE, "Wrote PI_RESET_CODE: {:08x}",
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processor_interface.m_ResetCode);
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processor_interface.m_reset_code);
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if (!SConfig::GetInstance().bWii && ~processor_interface.m_ResetCode & 0x4)
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if (!SConfig::GetInstance().bWii && ~processor_interface.m_reset_code & 0x4)
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{
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{
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DVDInterface::ResetDrive(true);
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DVDInterface::ResetDrive(true);
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}
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}
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@ -138,7 +139,7 @@ void ProcessorInterfaceManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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void ProcessorInterfaceManager::UpdateException()
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void ProcessorInterfaceManager::UpdateException()
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{
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{
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if ((m_InterruptCause & m_InterruptMask) != 0)
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if ((m_interrupt_cause & m_interrupt_mask) != 0)
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PowerPC::ppcState.Exceptions |= EXCEPTION_EXTERNAL_INT;
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PowerPC::ppcState.Exceptions |= EXCEPTION_EXTERNAL_INT;
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else
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else
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PowerPC::ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
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PowerPC::ppcState.Exceptions &= ~EXCEPTION_EXTERNAL_INT;
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@ -189,22 +190,22 @@ void ProcessorInterfaceManager::SetInterrupt(u32 cause_mask, bool set)
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{
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{
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DEBUG_ASSERT_MSG(POWERPC, Core::IsCPUThread(), "SetInterrupt from wrong thread");
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DEBUG_ASSERT_MSG(POWERPC, Core::IsCPUThread(), "SetInterrupt from wrong thread");
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if (set && !(m_InterruptCause & cause_mask))
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if (set && !(m_interrupt_cause & cause_mask))
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{
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{
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (set)",
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (set)",
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Debug_GetInterruptName(cause_mask));
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Debug_GetInterruptName(cause_mask));
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}
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}
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if (!set && (m_InterruptCause & cause_mask))
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if (!set && (m_interrupt_cause & cause_mask))
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{
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{
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (clear)",
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DEBUG_LOG_FMT(PROCESSORINTERFACE, "Setting Interrupt {} (clear)",
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Debug_GetInterruptName(cause_mask));
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Debug_GetInterruptName(cause_mask));
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}
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}
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if (set)
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if (set)
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m_InterruptCause |= cause_mask;
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m_interrupt_cause |= cause_mask;
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else
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else
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m_InterruptCause &= ~cause_mask; // is there any reason to have this possibility?
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m_interrupt_cause &= ~cause_mask; // is there any reason to have this possibility?
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// F|RES: i think the hw devices reset the interrupt in the PI to 0
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// F|RES: i think the hw devices reset the interrupt in the PI to 0
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// if the interrupt cause is eliminated. that isn't done by software (afaik)
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// if the interrupt cause is eliminated. that isn't done by software (afaik)
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UpdateException();
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UpdateException();
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@ -252,10 +253,11 @@ void ProcessorInterfaceManager::ResetButton_Tap()
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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auto& core_timing = system.GetCoreTiming();
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auto& core_timing = system.GetCoreTiming();
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core_timing.ScheduleEvent(0, toggleResetButton, true, CoreTiming::FromThread::ANY);
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core_timing.ScheduleEvent(0, m_event_type_toggle_reset_button, true, CoreTiming::FromThread::ANY);
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core_timing.ScheduleEvent(0, iosNotifyResetButton, 0, CoreTiming::FromThread::ANY);
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core_timing.ScheduleEvent(0, m_event_type_ios_notify_reset_button, 0,
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core_timing.ScheduleEvent(SystemTimers::GetTicksPerSecond() / 2, toggleResetButton, false,
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CoreTiming::FromThread::ANY);
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CoreTiming::FromThread::ANY);
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core_timing.ScheduleEvent(SystemTimers::GetTicksPerSecond() / 2, m_event_type_toggle_reset_button,
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false, CoreTiming::FromThread::ANY);
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}
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}
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void ProcessorInterfaceManager::PowerButton_Tap()
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void ProcessorInterfaceManager::PowerButton_Tap()
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@ -265,7 +267,8 @@ void ProcessorInterfaceManager::PowerButton_Tap()
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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auto& core_timing = system.GetCoreTiming();
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auto& core_timing = system.GetCoreTiming();
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core_timing.ScheduleEvent(0, iosNotifyPowerButton, 0, CoreTiming::FromThread::ANY);
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core_timing.ScheduleEvent(0, m_event_type_ios_notify_power_button, 0,
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CoreTiming::FromThread::ANY);
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}
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}
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} // namespace ProcessorInterface
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} // namespace ProcessorInterface
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@ -68,8 +68,8 @@ public:
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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u32 GetMask() const { return m_InterruptMask; }
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u32 GetMask() const { return m_interrupt_mask; }
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u32 GetCause() const { return m_InterruptCause; }
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u32 GetCause() const { return m_interrupt_cause; }
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void SetInterrupt(u32 cause_mask, bool set = true);
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void SetInterrupt(u32 cause_mask, bool set = true);
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@ -77,13 +77,13 @@ public:
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void ResetButton_Tap();
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void ResetButton_Tap();
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void PowerButton_Tap();
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void PowerButton_Tap();
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u32 m_InterruptCause = 0;
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u32 m_interrupt_cause = 0;
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u32 m_InterruptMask = 0;
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u32 m_interrupt_mask = 0;
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// addresses for CPU fifo accesses
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// addresses for CPU fifo accesses
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u32 Fifo_CPUBase = 0;
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u32 m_fifo_cpu_base = 0;
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u32 Fifo_CPUEnd = 0;
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u32 m_fifo_cpu_end = 0;
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u32 Fifo_CPUWritePointer = 0;
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u32 m_fifo_cpu_write_pointer = 0;
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private:
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private:
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// Let the PPC know that an external exception is set/cleared
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// Let the PPC know that an external exception is set/cleared
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@ -96,10 +96,10 @@ private:
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static void IOSNotifyResetButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate);
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static void IOSNotifyResetButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate);
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static void IOSNotifyPowerButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate);
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static void IOSNotifyPowerButtonCallback(Core::System& system, u64 userdata, s64 cyclesLate);
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CoreTiming::EventType* toggleResetButton = nullptr;
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CoreTiming::EventType* m_event_type_toggle_reset_button = nullptr;
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CoreTiming::EventType* iosNotifyResetButton = nullptr;
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CoreTiming::EventType* m_event_type_ios_notify_reset_button = nullptr;
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CoreTiming::EventType* iosNotifyPowerButton = nullptr;
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CoreTiming::EventType* m_event_type_ios_notify_power_button = nullptr;
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u32 m_ResetCode = 0;
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u32 m_reset_code = 0;
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};
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};
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} // namespace ProcessorInterface
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} // namespace ProcessorInterface
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@ -1045,7 +1045,7 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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TEST(32, PPCSTATE(msr), Imm32(0x0008000));
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TEST(32, PPCSTATE(msr), Imm32(0x0008000));
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FixupBranch noExtIntEnable = J_CC(CC_Z, true);
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FixupBranch noExtIntEnable = J_CC(CC_Z, true);
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_InterruptCause));
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MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_interrupt_cause));
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TEST(32, MatR(RSCRATCH),
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TEST(32, MatR(RSCRATCH),
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Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN |
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Imm32(ProcessorInterface::INT_CAUSE_CP | ProcessorInterface::INT_CAUSE_PE_TOKEN |
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ProcessorInterface::INT_CAUSE_PE_FINISH));
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ProcessorInterface::INT_CAUSE_PE_FINISH));
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@ -453,7 +453,7 @@ void Jit64::mtmsr(UGeckoInstruction inst)
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|
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// Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336)
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// Check if a CP interrupt is waiting and keep the GPU emulation in sync (issue 4336)
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_InterruptCause));
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MOV(64, R(RSCRATCH), ImmPtr(&system.GetProcessorInterface().m_interrupt_cause));
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TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP));
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TEST(32, MatR(RSCRATCH), Imm32(ProcessorInterface::INT_CAUSE_CP));
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FixupBranch cpInt = J_CC(CC_NZ);
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FixupBranch cpInt = J_CC(CC_NZ);
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@ -981,7 +981,7 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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TBZ(ARM64Reg::W30, 15, done_here); // MSR.EE
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TBZ(ARM64Reg::W30, 15, done_here); // MSR.EE
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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LDR(IndexType::Unsigned, ARM64Reg::W30, ARM64Reg::X30,
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LDR(IndexType::Unsigned, ARM64Reg::W30, ARM64Reg::X30,
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MOVPage2R(ARM64Reg::X30, &system.GetProcessorInterface().m_InterruptCause));
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MOVPage2R(ARM64Reg::X30, &system.GetProcessorInterface().m_interrupt_cause));
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constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP |
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constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP |
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ProcessorInterface::INT_CAUSE_PE_TOKEN |
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ProcessorInterface::INT_CAUSE_PE_TOKEN |
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ProcessorInterface::INT_CAUSE_PE_FINISH;
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ProcessorInterface::INT_CAUSE_PE_FINISH;
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@ -1018,7 +1018,7 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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TBZ(WA, 15, done_here); // MSR.EE
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TBZ(WA, 15, done_here); // MSR.EE
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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LDR(IndexType::Unsigned, WA, XA,
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LDR(IndexType::Unsigned, WA, XA,
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MOVPage2R(XA, &system.GetProcessorInterface().m_InterruptCause));
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MOVPage2R(XA, &system.GetProcessorInterface().m_interrupt_cause));
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constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP |
|
constexpr u32 cause_mask = ProcessorInterface::INT_CAUSE_CP |
|
||||||
ProcessorInterface::INT_CAUSE_PE_TOKEN |
|
ProcessorInterface::INT_CAUSE_PE_TOKEN |
|
||||||
ProcessorInterface::INT_CAUSE_PE_FINISH;
|
ProcessorInterface::INT_CAUSE_PE_FINISH;
|
||||||
|
@ -372,8 +372,8 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system)
|
|||||||
{
|
{
|
||||||
// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
|
// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
|
||||||
// Fix Pokemon XD in DC mode.
|
// Fix Pokemon XD in DC mode.
|
||||||
if ((processor_interface.Fifo_CPUEnd == fifo.CPEnd.load(std::memory_order_relaxed)) &&
|
if ((processor_interface.m_fifo_cpu_end == fifo.CPEnd.load(std::memory_order_relaxed)) &&
|
||||||
(processor_interface.Fifo_CPUBase == fifo.CPBase.load(std::memory_order_relaxed)) &&
|
(processor_interface.m_fifo_cpu_base == fifo.CPBase.load(std::memory_order_relaxed)) &&
|
||||||
fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > 0)
|
fifo.CPReadWriteDistance.load(std::memory_order_relaxed) > 0)
|
||||||
{
|
{
|
||||||
system.GetFifo().FlushGpu(system);
|
system.GetFifo().FlushGpu(system);
|
||||||
@ -396,9 +396,10 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system)
|
|||||||
|
|
||||||
if (m_cp_ctrl_reg.GPReadEnable && m_cp_ctrl_reg.GPLinkEnable)
|
if (m_cp_ctrl_reg.GPReadEnable && m_cp_ctrl_reg.GPLinkEnable)
|
||||||
{
|
{
|
||||||
processor_interface.Fifo_CPUWritePointer = fifo.CPWritePointer.load(std::memory_order_relaxed);
|
processor_interface.m_fifo_cpu_write_pointer =
|
||||||
processor_interface.Fifo_CPUBase = fifo.CPBase.load(std::memory_order_relaxed);
|
fifo.CPWritePointer.load(std::memory_order_relaxed);
|
||||||
processor_interface.Fifo_CPUEnd = fifo.CPEnd.load(std::memory_order_relaxed);
|
processor_interface.m_fifo_cpu_base = fifo.CPBase.load(std::memory_order_relaxed);
|
||||||
|
processor_interface.m_fifo_cpu_end = fifo.CPEnd.load(std::memory_order_relaxed);
|
||||||
}
|
}
|
||||||
|
|
||||||
// If the game is running close to overflowing, make the exception checking more frequent.
|
// If the game is running close to overflowing, make the exception checking more frequent.
|
||||||
@ -418,13 +419,13 @@ void CommandProcessorManager::GatherPipeBursted(Core::System& system)
|
|||||||
// check if we are in sync
|
// check if we are in sync
|
||||||
ASSERT_MSG(COMMANDPROCESSOR,
|
ASSERT_MSG(COMMANDPROCESSOR,
|
||||||
fifo.CPWritePointer.load(std::memory_order_relaxed) ==
|
fifo.CPWritePointer.load(std::memory_order_relaxed) ==
|
||||||
processor_interface.Fifo_CPUWritePointer,
|
processor_interface.m_fifo_cpu_write_pointer,
|
||||||
"FIFOs linked but out of sync");
|
"FIFOs linked but out of sync");
|
||||||
ASSERT_MSG(COMMANDPROCESSOR,
|
ASSERT_MSG(COMMANDPROCESSOR,
|
||||||
fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.Fifo_CPUBase,
|
fifo.CPBase.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_base,
|
||||||
"FIFOs linked but out of sync");
|
"FIFOs linked but out of sync");
|
||||||
ASSERT_MSG(COMMANDPROCESSOR,
|
ASSERT_MSG(COMMANDPROCESSOR,
|
||||||
fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.Fifo_CPUEnd,
|
fifo.CPEnd.load(std::memory_order_relaxed) == processor_interface.m_fifo_cpu_end,
|
||||||
"FIFOs linked but out of sync");
|
"FIFOs linked but out of sync");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Reference in New Issue
Block a user