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Jit64/JitArm64: Check Breakpoints Before FPU Availability
CachedInterpreter already does it in the expected order.
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@ -1035,6 +1035,30 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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}
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else
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{
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auto& cpu = m_system.GetCPU();
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auto& power_pc = m_system.GetPowerPC();
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if (m_enable_debugging && power_pc.GetBreakPoints().IsAddressBreakPoint(op.address) &&
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!cpu.IsStepping())
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{
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gpr.Flush();
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fpr.Flush();
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MOV(32, PPCSTATE(pc), Imm32(op.address));
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ABI_PushRegistersAndAdjustStack({}, 0);
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ABI_CallFunctionP(PowerPC::CheckBreakPointsFromJIT, &power_pc);
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ABI_PopRegistersAndAdjustStack({}, 0);
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MOV(64, R(RSCRATCH), ImmPtr(cpu.GetStatePtr()));
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TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
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FixupBranch noBreakpoint = J_CC(CC_Z);
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Cleanup();
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MOV(32, PPCSTATE(npc), Imm32(op.address));
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SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount));
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JMP(asm_routines.dispatcher_exit, Jump::Near);
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SetJumpTarget(noBreakpoint);
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}
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if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound)
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{
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// This instruction uses FPU - needs to add FP exception bailout
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@ -1061,30 +1085,6 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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js.firstFPInstructionFound = true;
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}
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auto& cpu = m_system.GetCPU();
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auto& power_pc = m_system.GetPowerPC();
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if (m_enable_debugging && power_pc.GetBreakPoints().IsAddressBreakPoint(op.address) &&
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!cpu.IsStepping())
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{
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gpr.Flush();
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fpr.Flush();
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MOV(32, PPCSTATE(pc), Imm32(op.address));
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ABI_PushRegistersAndAdjustStack({}, 0);
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ABI_CallFunctionP(PowerPC::CheckBreakPointsFromJIT, &power_pc);
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ABI_PopRegistersAndAdjustStack({}, 0);
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MOV(64, R(RSCRATCH), ImmPtr(cpu.GetStatePtr()));
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TEST(32, MatR(RSCRATCH), Imm32(0xFFFFFFFF));
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FixupBranch noBreakpoint = J_CC(CC_Z);
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Cleanup();
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MOV(32, PPCSTATE(npc), Imm32(op.address));
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SUB(32, PPCSTATE(downcount), Imm32(js.downcountAmount));
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JMP(asm_routines.dispatcher_exit, Jump::Near);
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SetJumpTarget(noBreakpoint);
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}
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if (bJITRegisterCacheOff)
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{
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gpr.Flush();
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@ -1169,35 +1169,6 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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}
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else
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{
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if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound)
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{
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// This instruction uses FPU - needs to add FP exception bailout
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ARM64Reg WA = gpr.GetReg();
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(msr));
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FixupBranch b1 = TBNZ(WA, 13); // Test FP enabled bit
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far_addr);
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gpr.Flush(FlushMode::MaintainState, WA);
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fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, LogicalImm(EXCEPTION_FPU_UNAVAILABLE, GPRSize::B32));
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STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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gpr.Unlock(WA);
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WriteExceptionExit(js.compilerPC, false, true);
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SwitchToNearCode();
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SetJumpTarget(b1);
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js.firstFPInstructionFound = true;
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}
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if (m_enable_debugging && !cpu.IsStepping() &&
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m_system.GetPowerPC().GetBreakPoints().IsAddressBreakPoint(op.address))
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{
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@ -1228,6 +1199,35 @@ bool JitArm64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
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SetJumpTarget(no_breakpoint);
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}
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if ((opinfo->flags & FL_USE_FPU) && !js.firstFPInstructionFound)
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{
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// This instruction uses FPU - needs to add FP exception bailout
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ARM64Reg WA = gpr.GetReg();
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(msr));
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FixupBranch b1 = TBNZ(WA, 13); // Test FP enabled bit
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FixupBranch far_addr = B();
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SwitchToFarCode();
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SetJumpTarget(far_addr);
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gpr.Flush(FlushMode::MaintainState, WA);
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fpr.Flush(FlushMode::MaintainState, ARM64Reg::INVALID_REG);
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LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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ORR(WA, WA, LogicalImm(EXCEPTION_FPU_UNAVAILABLE, GPRSize::B32));
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STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(Exceptions));
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gpr.Unlock(WA);
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WriteExceptionExit(js.compilerPC, false, true);
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SwitchToNearCode();
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SetJumpTarget(b1);
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js.firstFPInstructionFound = true;
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}
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if (bJITRegisterCacheOff)
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{
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FlushCarry();
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