mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-15 13:57:57 -07:00
A bit more progress on JIT WIP.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1846 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
magumagu9
parent
ee3646cfb4
commit
4acda0096b
@ -262,6 +262,11 @@ InstLoc IRBuilder::FoldZeroOp(unsigned Opcode, unsigned extra) {
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CRCache[extra] = EmitZeroOp(LoadCR, extra);
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return CRCache[extra];
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}
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if (Opcode == LoadCTR) {
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if (!CTRCache)
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CTRCache = EmitZeroOp(LoadCTR, extra);
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return CTRCache;
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}
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return EmitZeroOp(Opcode, extra);
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}
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@ -301,6 +306,14 @@ InstLoc IRBuilder::FoldUOp(unsigned Opcode, InstLoc Op1, unsigned extra) {
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CRCacheStore[extra] = EmitUOp(StoreCR, Op1, extra);
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return CRCacheStore[extra];
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}
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if (Opcode == StoreCTR) {
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CTRCache = Op1;
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if (CTRCacheStore) {
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*CTRCacheStore = 0;
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}
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CTRCacheStore = EmitUOp(StoreCTR, Op1, extra);
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return CTRCacheStore;
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}
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if (Opcode == CompactMRegToPacked) {
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if (getOpcode(*Op1) == ExpandPackedToMReg)
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return getOp1(Op1);
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@ -331,6 +344,13 @@ InstLoc IRBuilder::FoldAdd(InstLoc Op1, InstLoc Op2) {
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return EmitBiOp(Add, Op1, Op2);
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}
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InstLoc IRBuilder::FoldSub(InstLoc Op1, InstLoc Op2) {
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if (isImm(*Op2)) {
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return FoldAdd(Op1, EmitIntConst(-GetImmValue(Op2)));
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}
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return EmitBiOp(Sub, Op1, Op2);
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}
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InstLoc IRBuilder::FoldAnd(InstLoc Op1, InstLoc Op2) {
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if (isImm(*Op1)) {
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if (isImm(*Op2))
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@ -432,6 +452,11 @@ InstLoc IRBuilder::FoldRol(InstLoc Op1, InstLoc Op2) {
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}
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InstLoc IRBuilder::FoldBranchCond(InstLoc Op1, InstLoc Op2) {
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if (isImm(*Op1)) {
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if (GetImmValue(Op1))
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return EmitBranchUncond(Op2);
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return 0;
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}
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if (getOpcode(*Op1) == And &&
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isImm(*getOp2(Op1)) &&
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getOpcode(*getOp1(Op1)) == ICmpCRSigned) {
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@ -460,6 +485,71 @@ InstLoc IRBuilder::FoldBranchCond(InstLoc Op1, InstLoc Op2) {
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return EmitBiOp(BranchCond, Op1, Op2);
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}
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InstLoc IRBuilder::FoldICmp(unsigned Opcode, InstLoc Op1, InstLoc Op2) {
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if (isImm(*Op1)) {
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if (isImm(*Op2)) {
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unsigned result = 0;
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switch (Opcode) {
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case ICmpEq:
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result = GetImmValue(Op1) == GetImmValue(Op2);
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break;
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case ICmpUgt:
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result = GetImmValue(Op1) > GetImmValue(Op2);
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break;
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case ICmpUlt:
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result = GetImmValue(Op1) < GetImmValue(Op2);
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break;
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case ICmpUge:
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result = GetImmValue(Op1) >= GetImmValue(Op2);
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break;
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case ICmpUle:
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result = GetImmValue(Op1) <= GetImmValue(Op2);
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break;
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case ICmpSgt:
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result = (signed)GetImmValue(Op1) >
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(signed)GetImmValue(Op2);
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break;
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case ICmpSlt:
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result = (signed)GetImmValue(Op1) <
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(signed)GetImmValue(Op2);
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break;
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case ICmpSge:
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result = (signed)GetImmValue(Op1) >=
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(signed)GetImmValue(Op2);
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break;
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case ICmpSle:
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result = (signed)GetImmValue(Op1) <=
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(signed)GetImmValue(Op2);
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break;
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}
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return EmitIntConst(result);
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}
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switch (Opcode) {
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case ICmpEq:
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return FoldICmp(ICmpEq, Op2, Op1);
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case ICmpNe:
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return FoldICmp(ICmpNe, Op2, Op1);
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case ICmpUlt:
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return FoldICmp(ICmpUgt, Op2, Op1);
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case ICmpUgt:
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return FoldICmp(ICmpUlt, Op2, Op1);
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case ICmpUle:
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return FoldICmp(ICmpUge, Op2, Op1);
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case ICmpUge:
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return FoldICmp(ICmpUle, Op2, Op1);
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case ICmpSlt:
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return FoldICmp(ICmpSgt, Op2, Op1);
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case ICmpSgt:
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return FoldICmp(ICmpSlt, Op2, Op1);
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case ICmpSle:
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return FoldICmp(ICmpSge, Op2, Op1);
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case ICmpSge:
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return FoldICmp(ICmpSle, Op2, Op1);
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}
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}
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return EmitBiOp(Opcode, Op1, Op2);
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}
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InstLoc IRBuilder::FoldInterpreterFallback(InstLoc Op1, InstLoc Op2) {
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for (unsigned i = 0; i < 32; i++) {
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GRegCache[i] = 0;
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@ -473,12 +563,15 @@ InstLoc IRBuilder::FoldInterpreterFallback(InstLoc Op1, InstLoc Op2) {
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CRCache[i] = 0;
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CRCacheStore[i] = 0;
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}
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CTRCache = 0;
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CTRCacheStore = 0;
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return EmitBiOp(InterpreterFallback, Op1, Op2);
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}
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InstLoc IRBuilder::FoldBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2, unsigned extra) {
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switch (Opcode) {
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case Add: return FoldAdd(Op1, Op2);
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case Sub: return FoldSub(Op1, Op2);
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case And: return FoldAnd(Op1, Op2);
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case Or: return FoldOr(Op1, Op2);
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case Xor: return FoldXor(Op1, Op2);
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@ -486,6 +579,10 @@ InstLoc IRBuilder::FoldBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2, unsigned
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case Shrl: return FoldShrl(Op1, Op2);
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case Rol: return FoldRol(Op1, Op2);
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case BranchCond: return FoldBranchCond(Op1, Op2);
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case ICmpEq: case ICmpNe:
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case ICmpUgt: case ICmpUlt: case ICmpUge: case ICmpUle:
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case ICmpSgt: case ICmpSlt: case ICmpSge: case ICmpSle:
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return FoldICmp(Opcode, Op1, Op2);
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case InterpreterFallback: return FoldInterpreterFallback(Op1, Op2);
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default: return EmitBiOp(Opcode, Op1, Op2, extra);
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}
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@ -738,8 +835,19 @@ static void fregNormalRegClear(RegInfo& RI, InstLoc I) {
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static void regEmitBinInst(RegInfo& RI, InstLoc I,
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void (Jit64::*op)(int, const OpArg&,
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const OpArg&)) {
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X64Reg reg = regBinLHSReg(RI, I);
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const OpArg&),
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bool commutable = false) {
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X64Reg reg;
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bool commuted = false;
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if (RI.IInfo[I - RI.FirstI] & 4) {
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reg = regEnsureInReg(RI, getOp1(I));
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} else if (commutable && (RI.IInfo[I - RI.FirstI] & 8)) {
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reg = regEnsureInReg(RI, getOp2(I));
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commuted = true;
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} else {
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reg = regFindFreeReg(RI);
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RI.Jit->MOV(32, R(reg), regLocForInst(RI, getOp1(I)));
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}
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if (isImm(*getOp2(I))) {
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unsigned RHS = RI.Build->GetImmValue(getOp2(I));
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if (RHS + 128 < 256) {
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@ -747,6 +855,8 @@ static void regEmitBinInst(RegInfo& RI, InstLoc I,
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} else {
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(RI.Jit->*op)(32, R(reg), Imm32(RHS));
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}
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} else if (commuted) {
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(RI.Jit->*op)(32, R(reg), regLocForInst(RI, getOp1(I)));
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} else {
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(RI.Jit->*op)(32, R(reg), regLocForInst(RI, getOp2(I)));
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}
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@ -754,6 +864,20 @@ static void regEmitBinInst(RegInfo& RI, InstLoc I,
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regNormalRegClear(RI, I);
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}
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static void fregEmitBinInst(RegInfo& RI, InstLoc I,
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void (Jit64::*op)(X64Reg, OpArg)) {
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X64Reg reg;
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if (RI.IInfo[I - RI.FirstI] & 4) {
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reg = fregEnsureInReg(RI, getOp1(I));
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} else {
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reg = fregFindFreeReg(RI);
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RI.Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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}
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(RI.Jit->*op)(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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}
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// Mark and calculation routines for profiled load/store addresses
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// Could be extended to unprofiled addresses.
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static void regMarkMemAddress(RegInfo& RI, InstLoc I, InstLoc AI, unsigned OpNum) {
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@ -994,6 +1118,15 @@ static void regEmitCmp(RegInfo& RI, InstLoc I) {
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}
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}
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static void regEmitICmpInst(RegInfo& RI, InstLoc I, CCFlags flag) {
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regEmitCmp(RI, I);
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RI.Jit->SETcc(flag, R(ECX)); // Caution: SETCC uses 8-bit regs!
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X64Reg reg = regFindFreeReg(RI);
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RI.Jit->MOVZX(32, 8, reg, R(ECX));
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RI.regs[reg] = I;
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regNormalRegClear(RI, I);
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}
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static void regWriteExit(RegInfo& RI, InstLoc dest) {
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if (RI.MakeProfile) {
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if (isImm(*dest)) {
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@ -1105,9 +1238,15 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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case ICmpCRUnsigned:
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case ICmpCRSigned:
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case ICmpEq:
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case ICmpNe:
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case ICmpUgt:
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case ICmpSle:
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case ICmpUlt:
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case ICmpUge:
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case ICmpUle:
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case ICmpSgt:
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case ICmpSlt:
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case ICmpSge:
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case ICmpSle:
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case FSMul:
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case FSAdd:
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case FSSub:
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@ -1311,12 +1450,12 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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}
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case And: {
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if (!thisUsed) break;
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regEmitBinInst(RI, I, &Jit64::AND);
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regEmitBinInst(RI, I, &Jit64::AND, true);
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break;
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}
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case Xor: {
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if (!thisUsed) break;
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regEmitBinInst(RI, I, &Jit64::XOR);
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regEmitBinInst(RI, I, &Jit64::XOR, true);
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break;
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}
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case Sub: {
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@ -1326,12 +1465,12 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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}
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case Or: {
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if (!thisUsed) break;
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regEmitBinInst(RI, I, &Jit64::OR);
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regEmitBinInst(RI, I, &Jit64::OR, true);
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break;
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}
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case Add: {
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if (!thisUsed) break;
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regEmitBinInst(RI, I, &Jit64::ADD);
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regEmitBinInst(RI, I, &Jit64::ADD, true);
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break;
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}
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case Mul: {
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@ -1374,32 +1513,52 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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}
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case ICmpEq: {
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if (!thisUsed) break;
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regEmitCmp(RI, I);
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Jit->SETcc(CC_Z, R(ECX)); // Caution: SETCC uses 8-bit regs!
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOVZX(32, 8, reg, R(ECX));
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RI.regs[reg] = I;
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regNormalRegClear(RI, I);
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regEmitICmpInst(RI, I, CC_E);
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break;
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}
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case ICmpNe: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_NE);
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break;
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}
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case ICmpUgt: {
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if (!thisUsed) break;
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regEmitCmp(RI, I);
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Jit->SETcc(CC_A, R(ECX)); // Caution: SETCC uses 8-bit regs!
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOVZX(32, 8, reg, R(ECX));
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RI.regs[reg] = I;
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regNormalRegClear(RI, I);
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regEmitICmpInst(RI, I, CC_A);
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break;
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}
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case ICmpUlt: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_B);
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break;
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}
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case ICmpUge: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_AE);
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break;
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}
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case ICmpUle: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_BE);
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break;
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}
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case ICmpSgt: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_G);
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break;
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}
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case ICmpSlt: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_L);
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break;
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}
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case ICmpSge: {
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if (!thisUsed) break;
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regEmitICmpInst(RI, I, CC_GE);
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break;
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}
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case ICmpSle: {
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if (!thisUsed) break;
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regEmitCmp(RI, I);
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Jit->SETcc(CC_LE, R(ECX)); // Caution: SETCC uses 8-bit regs!
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X64Reg reg = regFindFreeReg(RI);
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Jit->MOVZX(32, 8, reg, R(ECX));
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RI.regs[reg] = I;
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regNormalRegClear(RI, I);
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regEmitICmpInst(RI, I, CC_LE);
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break;
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}
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case ICmpCRUnsigned: {
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@ -1649,83 +1808,47 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
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}
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case FSMul: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->MULSS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::MULSS);
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break;
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}
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case FSAdd: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->ADDSS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::ADDSS);
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break;
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}
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case FSSub: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->SUBSS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::SUBSS);
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break;
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}
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case FDMul: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->MULSD(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::MULSD);
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break;
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}
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case FDAdd: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->ADDSD(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::ADDSD);
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break;
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}
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case FDSub: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->SUBSD(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::SUBSD);
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break;
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}
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case FPAdd: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->ADDPS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
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fregEmitBinInst(RI, I, &Jit64::ADDPS);
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break;
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}
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case FPMul: {
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if (!thisUsed) break;
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X64Reg reg = fregFindFreeReg(RI);
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Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
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Jit->MULPS(reg, fregLocForInst(RI, getOp2(I)));
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RI.fregs[reg] = I;
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fregNormalRegClear(RI, I);
|
||||
fregEmitBinInst(RI, I, &Jit64::MULPS);
|
||||
break;
|
||||
}
|
||||
case FPSub: {
|
||||
if (!thisUsed) break;
|
||||
X64Reg reg = fregFindFreeReg(RI);
|
||||
Jit->MOVAPD(reg, fregLocForInst(RI, getOp1(I)));
|
||||
Jit->SUBPS(reg, fregLocForInst(RI, getOp2(I)));
|
||||
RI.fregs[reg] = I;
|
||||
fregNormalRegClear(RI, I);
|
||||
fregEmitBinInst(RI, I, &Jit64::SUBPS);
|
||||
break;
|
||||
}
|
||||
case FPMerge00: {
|
||||
@ -1785,7 +1908,7 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
|
||||
isImm(*getOp2(getOp1(I)))) {
|
||||
Jit->CMP(32, regLocForInst(RI, getOp1(getOp1(I))),
|
||||
Imm32(RI.Build->GetImmValue(getOp2(getOp1(I)))));
|
||||
FixupBranch cont = Jit->J_CC(CC_Z);
|
||||
FixupBranch cont = Jit->J_CC(CC_NZ);
|
||||
regWriteExit(RI, getOp2(I));
|
||||
Jit->SetJumpTarget(cont);
|
||||
if (RI.IInfo[I - RI.FirstI] & 4)
|
||||
@ -1794,14 +1917,14 @@ static void DoWriteCode(IRBuilder* ibuild, Jit64* Jit, bool UseProfile) {
|
||||
isImm(*getOp2(getOp1(I)))) {
|
||||
Jit->CMP(32, regLocForInst(RI, getOp1(getOp1(I))),
|
||||
Imm32(RI.Build->GetImmValue(getOp2(getOp1(I)))));
|
||||
FixupBranch cont = Jit->J_CC(CC_LE);
|
||||
FixupBranch cont = Jit->J_CC(CC_G);
|
||||
regWriteExit(RI, getOp2(I));
|
||||
Jit->SetJumpTarget(cont);
|
||||
if (RI.IInfo[I - RI.FirstI] & 4)
|
||||
regClearInst(RI, getOp1(getOp1(I)));
|
||||
} else {
|
||||
Jit->CMP(32, regLocForInst(RI, getOp1(I)), Imm8(0));
|
||||
FixupBranch cont = Jit->J_CC(CC_NZ);
|
||||
FixupBranch cont = Jit->J_CC(CC_Z);
|
||||
regWriteExit(RI, getOp2(I));
|
||||
Jit->SetJumpTarget(cont);
|
||||
if (RI.IInfo[I - RI.FirstI] & 4)
|
||||
|
||||
@ -73,8 +73,14 @@ namespace IREmitter {
|
||||
ICmpCRSigned, // CR for signed int compare
|
||||
ICmpCRUnsigned, // CR for unsigned int compare
|
||||
ICmpEq, // One if equal, zero otherwise
|
||||
ICmpNe,
|
||||
ICmpUgt, // One if op1 > op2, zero otherwise
|
||||
ICmpUlt,
|
||||
ICmpUge,
|
||||
ICmpUle,
|
||||
ICmpSgt, // One if op1 > op2, zero otherwise
|
||||
ICmpSlt,
|
||||
ICmpSge,
|
||||
ICmpSle, // Opposite of sgt
|
||||
// Memory store operators
|
||||
Store8,
|
||||
@ -232,6 +238,7 @@ namespace IREmitter {
|
||||
unsigned extra = 0);
|
||||
|
||||
InstLoc FoldAdd(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldSub(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldAnd(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldOr(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldRol(InstLoc Op1, InstLoc Op2);
|
||||
@ -239,6 +246,7 @@ namespace IREmitter {
|
||||
InstLoc FoldShrl(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldXor(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldBranchCond(InstLoc Op1, InstLoc Op2);
|
||||
InstLoc FoldICmp(unsigned Opcode, InstLoc Op1, InstLoc Op2);
|
||||
|
||||
InstLoc FoldInterpreterFallback(InstLoc Op1, InstLoc Op2);
|
||||
|
||||
@ -502,6 +510,8 @@ namespace IREmitter {
|
||||
CRCache[i] = 0;
|
||||
CRCacheStore[i] = 0;
|
||||
}
|
||||
CTRCache = 0;
|
||||
CTRCacheStore = 0;
|
||||
}
|
||||
|
||||
IRBuilder() { Reset(); }
|
||||
@ -518,6 +528,8 @@ namespace IREmitter {
|
||||
InstLoc FRegCacheStore[32];
|
||||
InstLoc CarryCache;
|
||||
InstLoc CarryCacheStore;
|
||||
InstLoc CTRCache;
|
||||
InstLoc CTRCacheStore;
|
||||
InstLoc CRCache[8];
|
||||
InstLoc CRCacheStore[8];
|
||||
};
|
||||
|
||||
@ -434,16 +434,6 @@ namespace CPUCompare
|
||||
SetJumpTarget(b1);
|
||||
}
|
||||
|
||||
if (false && jo.fastInterrupts)
|
||||
{
|
||||
// This does NOT yet work.
|
||||
TEST(32, M(&PowerPC::ppcState.Exceptions), Imm32(0xFFFFFFFF));
|
||||
FixupBranch b1 = J_CC(CC_Z);
|
||||
MOV(32, M(&PC), Imm32(js.blockStart));
|
||||
JMP(asm_routines.testExceptions, true);
|
||||
SetJumpTarget(b1);
|
||||
}
|
||||
|
||||
js.rewriteStart = (u8*)GetCodePtr();
|
||||
|
||||
// Start up IR builder (structure that collects the
|
||||
@ -455,26 +445,13 @@ namespace CPUCompare
|
||||
// Translate instructions
|
||||
for (int i = 0; i < (int)size; i++)
|
||||
{
|
||||
// gpr.Flush(FLUSH_ALL);
|
||||
// if (PPCTables::UsesFPU(_inst))
|
||||
// fpr.Flush(FLUSH_ALL);
|
||||
js.compilerPC = ops[i].address;
|
||||
js.op = &ops[i];
|
||||
js.instructionNumber = i;
|
||||
if (i == (int)size - 1)
|
||||
{
|
||||
// WARNING - cmp->branch merging will screw this up.
|
||||
js.isLastInstruction = true;
|
||||
js.next_inst = 0;
|
||||
if (Profiler::g_ProfileBlocks) {
|
||||
// CAUTION!!! push on stack regs you use, do your stuff, then pop
|
||||
PROFILER_VPUSH;
|
||||
// get end tic
|
||||
PROFILER_QUERY_PERFORMACE_COUNTER(&b->ticStop);
|
||||
// tic counter += (end tic - start tic)
|
||||
PROFILER_ADD_DIFF_LARGE_INTEGER(&b->ticCounter, &b->ticStop, &b->ticStart);
|
||||
PROFILER_VPOP;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -483,25 +460,8 @@ namespace CPUCompare
|
||||
js.next_compilerPC = ops[i + 1].address;
|
||||
}
|
||||
|
||||
if (jo.optimizeGatherPipe && js.fifoBytesThisBlock >= 32)
|
||||
{
|
||||
js.fifoBytesThisBlock -= 32;
|
||||
ABI_CallFunction(thunks.ProtectFunction((void *)&GPFifo::CheckGatherPipe, 0));
|
||||
}
|
||||
|
||||
// If starting from the breakpointed instruction, we don't break.
|
||||
if (em_address != ops[i].address && BreakPoints::IsAddressBreakPoint(ops[i].address))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if (!ops[i].skip)
|
||||
PPCTables::CompileInstruction(ops[i].inst);
|
||||
|
||||
gpr.SanityCheck();
|
||||
fpr.SanityCheck();
|
||||
if (js.cancel)
|
||||
break;
|
||||
}
|
||||
|
||||
// Perform actual code generation
|
||||
|
||||
@ -84,7 +84,7 @@ using namespace Gen;
|
||||
IREmitter::InstLoc CRReg = ibuild.EmitLoadCR(inst.BI >> 2);
|
||||
IREmitter::InstLoc CRCmp = ibuild.EmitIntConst(8 >> (inst.BI & 3));
|
||||
CRTest = ibuild.EmitAnd(CRReg, CRCmp);
|
||||
if (inst.BO & 8)
|
||||
if (!(inst.BO & 8))
|
||||
CRTest = ibuild.EmitXor(CRTest, CRCmp);
|
||||
}
|
||||
|
||||
@ -92,7 +92,7 @@ using namespace Gen;
|
||||
IREmitter::InstLoc c = ibuild.EmitLoadCTR();
|
||||
c = ibuild.EmitSub(c, ibuild.EmitIntConst(1));
|
||||
ibuild.EmitStoreCTR(c);
|
||||
if (!(inst.BO & 2)) {
|
||||
if (inst.BO & 2) {
|
||||
CTRTest = ibuild.EmitICmpEq(c,
|
||||
ibuild.EmitIntConst(0));
|
||||
} else {
|
||||
@ -103,7 +103,7 @@ using namespace Gen;
|
||||
IREmitter::InstLoc Test = CRTest;
|
||||
if (CTRTest) {
|
||||
if (Test)
|
||||
Test = ibuild.EmitOr(Test, CTRTest);
|
||||
Test = ibuild.EmitAnd(Test, CTRTest);
|
||||
else
|
||||
Test = CTRTest;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user