mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 13:27:45 -07:00
use libogc for a bunch of headers instead of dspspy's random ones. (revert if they're used for a reason...)
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3227 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
parent
613aa198df
commit
4f0fbacd78
@ -114,14 +114,6 @@
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<References>
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</References>
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<Files>
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<File
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RelativePath=".\asm.h"
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>
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</File>
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<File
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RelativePath=".\color.h"
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>
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</File>
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<File
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RelativePath=".\Config.h"
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>
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@ -138,14 +130,6 @@
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RelativePath=".\display_font.cpp"
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>
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</File>
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<File
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RelativePath=".\dsp.h"
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>
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</File>
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<File
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RelativePath=".\irq.h"
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>
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</File>
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<File
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RelativePath=".\main_spy.cpp"
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>
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@ -162,10 +146,6 @@
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RelativePath=".\mem_dump.h"
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>
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</File>
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<File
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RelativePath=".\processor.h"
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>
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</File>
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<File
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RelativePath=".\Stubs.cpp"
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>
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@ -1,317 +0,0 @@
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#ifndef __ASM_H__
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#define __ASM_H__
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#ifdef _LANGUAGE_ASSEMBLY
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0 0
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#define r1 1
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#define sp 1
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#define r2 2
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#define toc 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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/* Floating Point Registers (FPRs) */
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#define fr0 0
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#define fr1 1
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#define fr2 2
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#define fr3 3
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#define fr4 4
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#define fr5 5
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#define fr6 6
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#define fr7 7
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#define fr8 8
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#define fr9 9
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#define fr10 10
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#define fr11 11
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#define fr12 12
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#define fr13 13
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#define fr14 14
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#define fr15 15
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#define fr16 16
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#define fr17 17
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#define fr18 18
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#define fr19 19
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#define fr20 20
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#define fr21 21
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#define fr22 22
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#define fr23 23
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#define fr24 24
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#define fr25 25
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#define fr26 26
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#define fr27 27
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#define fr28 28
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#define fr29 29
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#define fr30 30
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#define fr31 31
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#define vr0 0
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#define vr1 1
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#define vr2 2
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#define vr3 3
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#define vr4 4
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#define vr5 5
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#define vr6 6
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#define vr7 7
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#define vr8 8
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#define vr9 9
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#define vr10 10
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#define vr11 11
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#define vr12 12
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#define vr13 13
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#define vr14 14
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#define vr15 15
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#define vr16 16
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#define vr17 17
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#define vr18 18
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#define vr19 19
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#define vr20 20
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#define vr21 21
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#define vr22 22
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#define vr23 23
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#define vr24 24
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#define vr25 25
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#define vr26 26
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#define vr27 27
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#define vr28 28
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#define vr29 29
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#define vr30 30
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#define vr31 31
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#define SPRG0 272
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#define SPRG1 273
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#define SPRG2 274
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#define SPRG3 275
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#define PMC1 953
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#define PMC2 954
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#define PMC3 957
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#define PMC4 958
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#define MMCR0 952
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#define MMCR1 956
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#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
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#define EXCEPTION_NUMBER 8
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#define SRR0_OFFSET 12
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#define SRR1_OFFSET 16
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#define GPR0_OFFSET 20
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#define GPR1_OFFSET 24
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#define GPR2_OFFSET 28
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#define GPR3_OFFSET 32
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#define GPR4_OFFSET 36
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#define GPR5_OFFSET 40
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#define GPR6_OFFSET 44
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#define GPR7_OFFSET 48
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#define GPR8_OFFSET 52
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#define GPR9_OFFSET 56
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#define GPR10_OFFSET 60
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#define GPR11_OFFSET 64
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#define GPR12_OFFSET 68
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#define GPR13_OFFSET 72
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#define GPR14_OFFSET 76
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#define GPR15_OFFSET 80
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#define GPR16_OFFSET 84
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#define GPR17_OFFSET 88
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#define GPR18_OFFSET 92
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#define GPR19_OFFSET 96
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#define GPR20_OFFSET 100
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#define GPR21_OFFSET 104
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#define GPR22_OFFSET 108
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#define GPR23_OFFSET 112
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#define GPR24_OFFSET 116
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#define GPR25_OFFSET 120
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#define GPR26_OFFSET 124
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#define GPR27_OFFSET 128
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#define GPR28_OFFSET 132
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#define GPR29_OFFSET 136
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#define GPR30_OFFSET 140
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#define GPR31_OFFSET 144
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#define GQR0_OFFSET 148
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#define GQR1_OFFSET 152
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#define GQR2_OFFSET 156
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#define GQR3_OFFSET 160
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#define GQR4_OFFSET 164
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#define GQR5_OFFSET 168
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#define GQR6_OFFSET 172
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#define GQR7_OFFSET 176
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#define CR_OFFSET 180
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#define LR_OFFSET 184
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#define CTR_OFFSET 188
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#define XER_OFFSET 192
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#define MSR_OFFSET 196
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#define DAR_OFFSET 200
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#define STATE_OFFSET 204
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#define MODE_OFFSET 206
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#define FPR0_OFFSET 208
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#define FPR1_OFFSET 216
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#define FPR2_OFFSET 224
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#define FPR3_OFFSET 232
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#define FPR4_OFFSET 240
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#define FPR5_OFFSET 248
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#define FPR6_OFFSET 256
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#define FPR7_OFFSET 264
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#define FPR8_OFFSET 272
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#define FPR9_OFFSET 280
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#define FPR10_OFFSET 288
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#define FPR11_OFFSET 296
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#define FPR12_OFFSET 304
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#define FPR13_OFFSET 312
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#define FPR14_OFFSET 320
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#define FPR15_OFFSET 328
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#define FPR16_OFFSET 336
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#define FPR17_OFFSET 344
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#define FPR18_OFFSET 352
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#define FPR19_OFFSET 360
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#define FPR20_OFFSET 368
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#define FPR21_OFFSET 376
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#define FPR22_OFFSET 384
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#define FPR23_OFFSET 392
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#define FPR24_OFFSET 400
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#define FPR25_OFFSET 408
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#define FPR26_OFFSET 416
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#define FPR27_OFFSET 424
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#define FPR28_OFFSET 432
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#define FPR29_OFFSET 440
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#define FPR30_OFFSET 448
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#define FPR31_OFFSET 456
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#define FPSCR_OFFSET 464
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#define PSR0_OFFSET 472
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#define PSR1_OFFSET 480
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#define PSR2_OFFSET 488
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#define PSR3_OFFSET 496
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#define PSR4_OFFSET 504
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#define PSR5_OFFSET 512
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#define PSR6_OFFSET 520
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#define PSR7_OFFSET 528
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#define PSR8_OFFSET 536
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#define PSR9_OFFSET 544
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#define PSR10_OFFSET 552
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#define PSR11_OFFSET 560
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#define PSR12_OFFSET 568
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#define PSR13_OFFSET 576
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#define PSR14_OFFSET 584
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#define PSR15_OFFSET 592
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#define PSR16_OFFSET 600
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#define PSR17_OFFSET 608
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#define PSR18_OFFSET 616
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#define PSR19_OFFSET 624
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#define PSR20_OFFSET 632
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#define PSR21_OFFSET 640
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#define PSR22_OFFSET 648
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#define PSR23_OFFSET 656
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#define PSR24_OFFSET 664
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#define PSR25_OFFSET 672
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#define PSR26_OFFSET 680
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#define PSR27_OFFSET 688
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#define PSR28_OFFSET 696
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#define PSR29_OFFSET 704
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#define PSR30_OFFSET 712
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#define PSR31_OFFSET 720
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/*
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* maintain the EABI requested 8 bytes aligment
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* As SVR4 ABI requires 16, make it 16 (as some
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* exception may need more registers to be processed...)
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*/
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#define EXCEPTION_FRAME_END 728
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#define IBAT0U 528
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#define IBAT0L 529
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#define IBAT1U 530
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#define IBAT1L 531
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#define IBAT2U 532
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#define IBAT2L 533
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#define IBAT3U 534
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#define IBAT3L 535
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#define DBAT0U 536
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#define DBAT0L 537
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#define DBAT1U 538
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#define DBAT1L 538
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#define DBAT2U 540
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#define DBAT2L 541
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#define DBAT3U 542
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#define DBAT3L 543
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#define HID0 1008
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#define HID1 1009
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#define HID2 920
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#define GQR0 912
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#define GQR1 913
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#define GQR2 914
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#define GQR3 915
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#define GQR4 916
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#define GQR5 917
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#define GQR6 918
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#define GQR7 919
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#define L2CR 1017
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#define DMAU 922
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#define DMAL 923
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#endif //_LANGUAGE_ASSEMBLY
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#define MSR_RI 0x00000002
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#define MSR_DR 0x00000010
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#define MSR_IR 0x00000020
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#define MSR_IP 0x00000040
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#define MSR_SE 0x00000400
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#define MSR_ME 0x00001000
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#define MSR_FP 0x00002000
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#define MSR_POW 0x00004000
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#define MSR_EE 0x00008000
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#define PPC_ALIGNMENT 4
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#endif //__ASM_H__
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@ -1,28 +0,0 @@
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#ifndef __COLOR_H__
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#define __COLOR_H__
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// luminance is stored twice, thus one of the lum. is
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// redundant, but this way we can fill the screen.
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#define COLOR_BLACK (0x00800080)
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#define COLOR_MAROON (0x266A26C0)
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#define COLOR_GREEN (0x4B554B4A)
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#define COLOR_OLIVE (0x7140718A)
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#define COLOR_NAVY (0x0EC00E75)
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#define COLOR_PURPLE (0x34AA34B5)
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#define COLOR_TEAL (0x59955940)
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#define COLOR_GRAY (0x80808080)
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#define COLOR_SILVER (0xC080C080)
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#define COLOR_RED (0x4C544CFF)
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#define COLOR_LIME (0x952B9515)
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#define COLOR_YELLOW (0xE100E194)
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#define COLOR_BLUE (0x1DFF1D6B)
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#define COLOR_FUCHSIA (0x69D469EA)
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#define COLOR_AQUA (0xB2ABB200)
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#define COLOR_WHITE (0xFF80FF80)
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#define COLOR_MONEYGREEN (0xD076D074)
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#define COLOR_SKYBLUE (0xC399C36A)
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#define COLOR_CREAM (0xFA79FA82)
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#define COLOR_MEDGRAY (0xA082A07F)
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#endif /* COLOR_H */
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@ -8,9 +8,9 @@
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#undef errno
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extern int errno;
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#include "asm.h"
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#include "processor.h"
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#include "color.h"
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#include <ogc/color.h>
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#include <ogc/machine/asm.h>
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#include <ogc/machine/processor.h>
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#define FONT_XSIZE 8
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#define FONT_YSIZE 16
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@ -1,59 +0,0 @@
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#ifndef __DSP_H__
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#define __DSP_H__
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#include <gctypes.h>
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|
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#define DSPTASK_INIT 0
|
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#define DSPTASK_RUN 1
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#define DSPTASK_YIELD 2
|
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#define DSPTASK_DONE 3
|
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|
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#define DSPTASK_CLEARALL 0x00000000
|
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#define DSPTASK_ATTACH 0x00000001
|
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#define DSPTASK_CANCEL 0x00000002
|
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|
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#ifdef __cplusplus
|
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extern "C" {
|
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#endif /* __cplusplus */
|
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|
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typedef void (*DSPCallback)(void *task);
|
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|
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typedef struct _dsp_task {
|
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vu32 state;
|
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vu32 prio;
|
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vu32 flags;
|
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|
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u16 init_vec;
|
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u16 resume_vec;
|
||||
|
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u16 *iram_maddr;
|
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u32 iram_len;
|
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u16 iram_addr;
|
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|
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u16 *dram_maddr;
|
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u32 dram_len;
|
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u16 dram_addr;
|
||||
|
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DSPCallback init_cb;
|
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DSPCallback res_cb;
|
||||
DSPCallback done_cb;
|
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DSPCallback req_cb;
|
||||
|
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struct _dsp_task *next;
|
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struct _dsp_task *prev;
|
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} dsptask_t;
|
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|
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void DSP_Init();
|
||||
u32 DSP_CheckMailTo();
|
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u32 DSP_CheckMailFrom();
|
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u32 DSP_ReadMailFrom();
|
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void DSP_AssertInt();
|
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void DSP_SendMailTo(u32 mail);
|
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u32 DSP_ReadCPUtoDSP();
|
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dsptask_t* DSP_AddTask(dsptask_t *task);
|
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|
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#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
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@ -1,97 +0,0 @@
|
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#ifndef __IRQ_H__
|
||||
#define __IRQ_H__
|
||||
|
||||
#include <gctypes.h>
|
||||
#include "context.h"
|
||||
|
||||
#define IM_NONE (0x00000000)
|
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#define IRQ_MEM0 0
|
||||
#define IRQ_MEM1 1
|
||||
#define IRQ_MEM2 2
|
||||
#define IRQ_MEM3 3
|
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#define IRQ_MEMADDRESS 4
|
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#define IRQ_DSP_AI 5
|
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#define IRQ_DSP_ARAM 6
|
||||
#define IRQ_DSP_DSP 7
|
||||
#define IRQ_AI_AI 8
|
||||
#define IRQ_EXI0_EXI 9
|
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#define IRQ_EXI0_TC 10
|
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#define IRQ_EXI0_EXT 11
|
||||
#define IRQ_EXI1_EXI 12
|
||||
#define IRQ_EXI1_TC 13
|
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#define IRQ_EXI1_EXT 14
|
||||
#define IRQ_EXI2_EXI 15
|
||||
#define IRQ_EXI2_TC 16
|
||||
#define IRQ_PI_CP 17
|
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#define IRQ_PI_PETOKEN 18
|
||||
#define IRQ_PI_PEFINISH 19
|
||||
#define IRQ_PI_SI 20
|
||||
#define IRQ_PI_DI 21
|
||||
#define IRQ_PI_RSW 22
|
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#define IRQ_PI_ERROR 23
|
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#define IRQ_PI_VI 24
|
||||
#define IRQ_PI_DEBUG 25
|
||||
#define IRQ_PI_HSP 26
|
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#define IRQ_MAX 32
|
||||
|
||||
#define IRQMASK(irq) (0x80000000u>>irq)
|
||||
|
||||
#define IM_MEM0 IRQMASK(IRQ_MEM0)
|
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#define IM_MEM1 IRQMASK(IRQ_MEM1)
|
||||
#define IM_MEM2 IRQMASK(IRQ_MEM2)
|
||||
#define IM_MEM3 IRQMASK(IRQ_MEM3)
|
||||
#define IM_MEMADDRESS IRQMASK(IRQ_MEMADDRESS)
|
||||
#define IM_MEM (IM_MEM0|IM_MEM1|IM_MEM2|IM_MEM3|IM_MEMADDRESS)
|
||||
|
||||
#define IM_DSP_AI IRQMASK(IRQ_DSP_AI)
|
||||
#define IM_DSP_ARAM IRQMASK(IRQ_DSP_ARAM)
|
||||
#define IM_DSP_DSP IRQMASK(IRQ_DSP_DSP)
|
||||
#define IM_DSP (IM_DSP_AI|IM_DSP_ARAM|IM_DSP_DSP)
|
||||
|
||||
#define IM_AI_AI IRQMASK(IRQ_AI_AI)
|
||||
#define IM_AI (IRQ_AI_AI)
|
||||
|
||||
#define IM_EXI0_EXI IRQMASK(IRQ_EXI0_EXI)
|
||||
#define IM_EXI0_TC IRQMASK(IRQ_EXI0_TC)
|
||||
#define IM_EXI0_EXT IRQMASK(IRQ_EXI0_EXT)
|
||||
#define IM_EXI0 (IM_EXI0_EXI|IM_EXI0_TC|IM_EXI0_EXT)
|
||||
|
||||
#define IM_EXI1_EXI IRQMASK(IRQ_EXI1_EXI)
|
||||
#define IM_EXI1_TC IRQMASK(IRQ_EXI1_TC)
|
||||
#define IM_EXI1_EXT IRQMASK(IRQ_EXI1_EXT)
|
||||
#define IM_EXI1 (IM_EXI1_EXI|IM_EXI1_TC|IM_EXI1_EXT)
|
||||
|
||||
#define IM_EXI2_EXI IRQMASK(IRQ_EXI2_EXI)
|
||||
#define IM_EXI2_TC IRQMASK(IRQ_EXI2_TC)
|
||||
#define IM_EXI2 (IM_EXI2_EXI|IM_EXI2_TC)
|
||||
#define IM_EXI (IM_EXI0|IM_EXI1|IM_EXI2)
|
||||
|
||||
#define IM_PI_CP IRQMASK(IRQ_PI_CP)
|
||||
#define IM_PI_PETOKEN IRQMASK(IRQ_PI_PETOKEN)
|
||||
#define IM_PI_PEFINISH IRQMASK(IRQ_PI_PEFINISH)
|
||||
#define IM_PI_SI IRQMASK(IRQ_PI_SI)
|
||||
#define IM_PI_DI IRQMASK(IRQ_PI_DI)
|
||||
#define IM_PI_RSW IRQMASK(IRQ_PI_RSW)
|
||||
#define IM_PI_ERROR IRQMASK(IRQ_PI_ERROR)
|
||||
#define IM_PI_VI IRQMASK(IRQ_PI_VI)
|
||||
#define IM_PI_DEBUG IRQMASK(IRQ_PI_DEBUG)
|
||||
#define IM_PI_HSP IRQMASK(IRQ_PI_HSP)
|
||||
#define IM_PI (IM_PI_CP|IM_PI_PETOKEN|IM_PI_PEFINISH|IM_PI_SI|IM_PI_DI|IM_PI_RSW|IM_PI_ERROR|IM_PI_VI|IM_PI_DEBUG|IM_PI_HSP)
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
typedef void (raw_irq_handler_t)(u32,void *);
|
||||
|
||||
raw_irq_handler_t* IRQ_Request(u32 nIrq,raw_irq_handler_t *pHndl,void *pCtx);
|
||||
raw_irq_handler_t* IRQ_Free(u32 nIrq);
|
||||
raw_irq_handler_t* IRQ_GetHandler(u32 nIrq);
|
||||
u32 IRQ_Disable();
|
||||
void IRQ_Restore(u32 level);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif
|
||||
@ -10,19 +10,18 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <network.h>
|
||||
#include <ogcsys.h>
|
||||
#include <time.h>
|
||||
#include <fat.h>
|
||||
#include <fcntl.h>
|
||||
#include <ogc/color.h>
|
||||
#include <ogc/dsp.h>
|
||||
#include <ogc/irq.h>
|
||||
#include <ogc/machine/asm.h>
|
||||
#include <ogc/machine/processor.h>
|
||||
#include <wiiuse/wpad.h>
|
||||
|
||||
#include "color.h"
|
||||
#include "network.h"
|
||||
#include "dsp.h"
|
||||
#include "asm.h"
|
||||
#include "processor.h"
|
||||
#include "irq.h"
|
||||
#include "dsp.h"
|
||||
#include "display.h"
|
||||
|
||||
// Pull in some constants etc from DSPCore.
|
||||
|
||||
@ -1,98 +0,0 @@
|
||||
#ifndef __PROCESSOR_H__
|
||||
#define __PROCESSOR_H__
|
||||
|
||||
#include <gctypes.h>
|
||||
|
||||
#define __stringify(rn) #rn
|
||||
#define ATTRIBUTE_ALIGN(v) __attribute__((aligned(v)))
|
||||
|
||||
#define ppcsync() asm volatile("sc")
|
||||
#define ppchalt() ({ \
|
||||
asm volatile("sync"); \
|
||||
while(1) { \
|
||||
asm volatile("nop"); \
|
||||
asm volatile("li 3,0"); \
|
||||
asm volatile("nop"); \
|
||||
} \
|
||||
})
|
||||
|
||||
#define mfdcr(_rn) ({register u32 _rval; \
|
||||
asm volatile("mfdcr %0," __stringify(_rn) \
|
||||
: "=r" (_rval)); _rval;})
|
||||
#define mtdcr(rn, val) asm volatile("mtdcr " __stringify(rn) ",%0" : : "r" (val))
|
||||
|
||||
#define mfmsr() ({register u32 _rval; \
|
||||
asm volatile("mfmsr %0" : "=r" (_rval)); _rval;})
|
||||
#define mtmsr(val) asm volatile("mtmsr %0" : : "r" (val))
|
||||
|
||||
#define mfdec() ({register u32 _rval; \
|
||||
asm volatile("mfdec %0" : "=r" (_rval)); _rval;})
|
||||
#define mtdec(_val) asm volatile("mtdec %0" : : "r" (_val))
|
||||
|
||||
#define mfspr(_rn) ({register u32 _rval; \
|
||||
asm volatile("mfspr %0," __stringify(_rn) \
|
||||
: "=r" (_rval)); _rval;})
|
||||
#define mtspr(_rn, _val) asm volatile("mtspr " __stringify(_rn) ",%0" : : "r" (_val))
|
||||
|
||||
#define mfwpar() mfspr(921)
|
||||
#define mtwpar(_val) mtspr(921,_val)
|
||||
|
||||
#define mfmmcr0() mfspr(952)
|
||||
#define mtmmcr0(_val) mtspr(952,_val)
|
||||
#define mfmmcr1() mfspr(956)
|
||||
#define mtmmcr1(_val) mtspr(956,_val)
|
||||
|
||||
#define mfpmc1() mfspr(953)
|
||||
#define mtpmc1(_val) mtspr(953,_val)
|
||||
#define mfpmc2() mfspr(954)
|
||||
#define mtpmc2(_val) mtspr(954,_val)
|
||||
#define mfpmc3() mfspr(957)
|
||||
#define mtpmc3(_val) mtspr(957,_val)
|
||||
#define mfpmc4() mfspr(958)
|
||||
#define mtpmc4(_val) mtspr(958,_val)
|
||||
|
||||
#define cntlzw(_val) ({register u32 _rval; \
|
||||
asm volatile("cntlzw %0, %1" : "=r"((_rval)) : "r"((_val))); _rval;})
|
||||
|
||||
#define _CPU_MSR_GET( _msr_value ) \
|
||||
do { \
|
||||
_msr_value = 0; \
|
||||
asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
|
||||
} while (0)
|
||||
|
||||
#define _CPU_MSR_SET( _msr_value ) \
|
||||
{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
|
||||
|
||||
#define _CPU_ISR_Enable() \
|
||||
{ register u32 _val = 0; \
|
||||
asm volatile ("mfmsr %0; ori %0,%0,0x8000; mtmsr %0" : \
|
||||
"=&r" (_val) : "0" (_val));\
|
||||
}
|
||||
|
||||
#define _CPU_ISR_Disable( _isr_cookie ) \
|
||||
{ register u32 _disable_mask = MSR_EE; \
|
||||
_isr_cookie = 0; \
|
||||
asm volatile ( \
|
||||
"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
|
||||
"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
|
||||
"0" ((_isr_cookie)), "1" ((_disable_mask)) \
|
||||
); \
|
||||
}
|
||||
|
||||
#define _CPU_ISR_Restore( _isr_cookie ) \
|
||||
{ \
|
||||
asm volatile ( "mtmsr %0" : \
|
||||
"=r" ((_isr_cookie)) : \
|
||||
"0" ((_isr_cookie))); \
|
||||
}
|
||||
|
||||
#define _CPU_ISR_Flash( _isr_cookie ) \
|
||||
{ register u32 _disable_mask = MSR_EE; \
|
||||
asm volatile ( \
|
||||
"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
|
||||
"=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
|
||||
"0" ((_isr_cookie)), "1" ((_disable_mask)) \
|
||||
); \
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user