mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 21:37:52 -07:00
code style cleanup for bba which has been sitting around my hdd for a long time
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@3944 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
parent
fa731c0b29
commit
5013ab957c
@ -16,6 +16,7 @@
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// http://code.google.com/p/dolphin-emu/
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#include <assert.h>
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#include "StringUtil.h"
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#include "../Memmap.h"
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// GROSS CODE ALERT: headers need to be included in the following order
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#include "TAP_Win32.h"
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@ -162,16 +163,17 @@ bool GetGUID(char *name, int name_size)
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bool CEXIETHERNET::deactivate()
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{
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DEBUGPRINT("Deactivating BBA...\n");
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if(!isActivated())
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DEBUGPRINT("Deactivating BBA...");
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if (!isActivated())
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return true;
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CloseHandle(mHRecvEvent);
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mHRecvEvent = INVALID_HANDLE_VALUE;
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CloseHandle(mHAdapter);
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mHAdapter = INVALID_HANDLE_VALUE;
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DEBUGPRINT("Success!\n");
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DEBUGPRINT("Success!");
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return true;
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}
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bool CEXIETHERNET::isActivated()
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{
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return mHAdapter != INVALID_HANDLE_VALUE;
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@ -179,11 +181,10 @@ bool CEXIETHERNET::isActivated()
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bool CEXIETHERNET::activate()
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{
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if (isActivated())
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return true;
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DEBUGPRINT("\nActivating BBA...\n");
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DEBUGPRINT("Activating BBA...");
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DWORD len;
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char device_path[256];
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@ -209,7 +210,7 @@ bool CEXIETHERNET::activate()
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if (mHAdapter == INVALID_HANDLE_VALUE)
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{
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DEBUGPRINT("Failed to open TAP at %s\n", device_path);
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DEBUGPRINT("Failed to open TAP at %s", device_path);
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return false;
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}
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@ -219,14 +220,14 @@ bool CEXIETHERNET::activate()
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if (DeviceIoControl (mHAdapter, TAP_IOCTL_GET_VERSION,
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&info, sizeof (info), &info, sizeof (info), &len, NULL))
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{
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DEBUGPRINT("TAP-Win32 Driver Version %d.%d %s\n",
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DEBUGPRINT("TAP-Win32 Driver Version %d.%d %s",
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info[0], info[1], (info[2] ? "(DEBUG)" : ""));
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}
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if ( !(info[0] > TAP_WIN32_MIN_MAJOR
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|| (info[0] == TAP_WIN32_MIN_MAJOR && info[1] >= TAP_WIN32_MIN_MINOR)) )
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{
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#define PACKAGE_NAME "Dolphin"
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DEBUGPRINT("ERROR: This version of " PACKAGE_NAME " requires a TAP-Win32 driver that is at least version %d.%d -- If you recently upgraded your " PACKAGE_NAME " distribution, a reboot is probably required at this point to get Windows to see the new driver.\n",
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DEBUGPRINT("ERROR: This version of " PACKAGE_NAME " requires a TAP-Win32 driver that is at least version %d.%d -- If you recently upgraded your " PACKAGE_NAME " distribution, a reboot is probably required at this point to get Windows to see the new driver.",
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TAP_WIN32_MIN_MAJOR,
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TAP_WIN32_MIN_MINOR);
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return false;
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@ -235,13 +236,13 @@ bool CEXIETHERNET::activate()
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/* get driver MTU */
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{
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if(!DeviceIoControl(mHAdapter, TAP_IOCTL_GET_MTU,
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if (!DeviceIoControl(mHAdapter, TAP_IOCTL_GET_MTU,
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&mMtu, sizeof (mMtu), &mMtu, sizeof (mMtu), &len, NULL))
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{
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DEBUGPRINT("Couldn't get device MTU");
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return false;
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}
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DEBUGPRINT("TAP-Win32 MTU=%d (ignored)\n", mMtu);
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DEBUGPRINT("TAP-Win32 MTU=%d (ignored)", mMtu);
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}
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/* set driver media status to 'connected' */
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@ -250,12 +251,12 @@ bool CEXIETHERNET::activate()
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if (!DeviceIoControl (mHAdapter, TAP_IOCTL_SET_MEDIA_STATUS,
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&status, sizeof (status), &status, sizeof (status), &len, NULL))
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{
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DEBUGPRINT("WARNING: The TAP-Win32 driver rejected a TAP_IOCTL_SET_MEDIA_STATUS DeviceIoControl call.\n");
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DEBUGPRINT("WARNING: The TAP-Win32 driver rejected a TAP_IOCTL_SET_MEDIA_STATUS DeviceIoControl call.");
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return false;
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}
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else
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{
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DEBUGPRINT("TAP-WIN32 status as Connected\n");
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DEBUGPRINT("TAP-WIN32 status as Connected");
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}
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}
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@ -264,54 +265,55 @@ bool CEXIETHERNET::activate()
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memset((void*)&mReadOverlapped, 0 , sizeof(mReadOverlapped));
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resume();
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DEBUGPRINT("Success!\n\n");
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DEBUGPRINT("Success!");
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return true;
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//TODO: Activate Device!
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}
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bool CEXIETHERNET::CheckRecieved()
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{
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if(!isActivated())
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if (!isActivated())
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return false;
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// I have no idea o_O
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return false;
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}
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bool CEXIETHERNET::sendPacket(u8 *etherpckt, int size)
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{
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if(!isActivated())
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if (!isActivated())
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activate();
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DEBUGPRINT( "Packet: 0x");
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for(int a = 0; a < size; ++a)
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{
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DEBUGPRINT( "%02X", etherpckt[a]);
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}
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DEBUGPRINT( " : Size: %d\n", size);
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DEBUGPRINT("Packet (%i): %s", size, ArrayToString(etherpckt, size).c_str());
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DWORD numBytesWrit;
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OVERLAPPED overlap;
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memset((void*)&overlap, 0, sizeof(overlap));
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//ZERO_OBJECT(overlap);
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//overlap.hEvent = mHRecvEvent;
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if(!WriteFile(mHAdapter, etherpckt, size, &numBytesWrit, &overlap))
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{ // Fail Boat
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DWORD res = GetLastError();
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DEBUGPRINT("Failed to send packet with error 0x%X\n", res);
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}
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if(numBytesWrit != size)
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if (!WriteFile(mHAdapter, etherpckt, size, &numBytesWrit, &overlap))
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{
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DEBUGPRINT("BBA sendPacket %i only got %i bytes sent!\n", size, numBytesWrit);
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// Fail Boat
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DWORD res = GetLastError();
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DEBUGPRINT("Failed to send packet with error 0x%X", res);
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}
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if (numBytesWrit != size)
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{
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DEBUGPRINT("BBA sendPacket %i only got %i bytes sent!", size, numBytesWrit);
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return false;
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}
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recordSendComplete();
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//exit(0);
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return true;
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}
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bool CEXIETHERNET::handleRecvdPacket()
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{
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int rbwpp = mCbw.p_write() + CB_OFFSET; //read buffer write page pointer
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u32 available_bytes_in_cb;
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if(rbwpp < mRBRPP)
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if (rbwpp < mRBRPP)
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available_bytes_in_cb = mRBRPP - rbwpp;
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else if(rbwpp == mRBRPP)
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else if (rbwpp == mRBRPP)
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available_bytes_in_cb = mRBEmpty ? CB_SIZE : 0;
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else //rbwpp > mRBRPP
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available_bytes_in_cb = CB_SIZE - rbwpp + (mRBRPP - CB_OFFSET);
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@ -321,7 +323,7 @@ bool CEXIETHERNET::handleRecvdPacket()
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//DUMPWORD(available_bytes_in_cb);
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assert(available_bytes_in_cb <= CB_SIZE);
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if(available_bytes_in_cb != CB_SIZE)//< mRecvBufferLength + SIZEOF_RECV_DESCRIPTOR)
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if (available_bytes_in_cb != CB_SIZE)//< mRecvBufferLength + SIZEOF_RECV_DESCRIPTOR)
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return true;
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cbwriteDescriptor(mRecvBufferLength);
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mCbw.write(mRecvBuffer, mRecvBufferLength);
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@ -332,69 +334,94 @@ bool CEXIETHERNET::handleRecvdPacket()
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//mPacketsRcvd++;
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mRecvBufferLength = 0;
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if(mBbaMem[0x08] & BBA_INTERRUPT_RECV)
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if (mBbaMem[0x08] & BBA_INTERRUPT_RECV)
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{
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if(!(mBbaMem[0x09] & BBA_INTERRUPT_RECV))
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if (!(mBbaMem[0x09] & BBA_INTERRUPT_RECV))
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{
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mBbaMem[0x09] |= BBA_INTERRUPT_RECV;
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DEBUGPRINT("BBA Recv interrupt raised\n");
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DEBUGPRINT("BBA Recv interrupt raised");
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//interrupt.raiseEXI("BBA Recv");
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m_bInterruptSet = true;
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}
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}
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if(mBbaMem[BBA_NCRA] & BBA_NCRA_SR)
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{
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if (mBbaMem[BBA_NCRA] & BBA_NCRA_SR)
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startRecv();
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return true;
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}
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bool CEXIETHERNET::resume()
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{
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if(!isActivated())
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return true;
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DEBUGPRINT("BBA resume");
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//mStop = false;
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RegisterWaitForSingleObject(&mHReadWait, mHRecvEvent, ReadWaitCallback,
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this, INFINITE, WT_EXECUTEDEFAULT);//WT_EXECUTEINWAITTHREAD
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mReadOverlapped.hEvent = mHRecvEvent;
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if (mBbaMem[BBA_NCRA] & BBA_NCRA_SR)
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startRecv();
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DEBUGPRINT("BBA resume complete");
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return true;
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}
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bool CEXIETHERNET::startRecv()
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{
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if (!isActivated())
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return false;// Should actually be an assert
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DEBUGPRINT("startRecv... ");
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if (mWaiting)
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{
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DEBUGPRINT("already waiting");
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return true;
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}
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DWORD res = ReadFile(mHAdapter, mRecvBuffer, mRecvBuffer.size(),
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&mRecvBufferLength, &mReadOverlapped);
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if (res)
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{
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// Operation completed immediately
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DEBUGPRINT("completed, res %i", res);
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mWaiting = true;
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}
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else
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{
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res = GetLastError();
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if (res == ERROR_IO_PENDING)
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{
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//'s ok :)
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DEBUGPRINT("pending");
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// WaitCallback will be called
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mWaiting = true;
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}
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else
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{
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// error occurred
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return false;
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}
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}
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return true;
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}
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bool CEXIETHERNET::resume() {
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if(!isActivated())
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return true;
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DEBUGPRINT("BBA resume\n");
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//mStop = false;
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RegisterWaitForSingleObject(&mHReadWait, mHRecvEvent, ReadWaitCallback,
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this, INFINITE, WT_EXECUTEDEFAULT);//WT_EXECUTEINWAITTHREAD
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mReadOverlapped.hEvent = mHRecvEvent;
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if(mBbaMem[BBA_NCRA] & BBA_NCRA_SR) {
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startRecv();
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}
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DEBUGPRINT("BBA resume complete\n");
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return true;
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}
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bool CEXIETHERNET::startRecv() {
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if(!isActivated())
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return false;// Should actually be an assert
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DEBUGPRINT("startRecv... ");
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if(mWaiting) {
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DEBUGPRINT("already waiting\n");
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return true;
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}
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DWORD res = ReadFile(mHAdapter, mRecvBuffer, mRecvBuffer.size(),
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&mRecvBufferLength, &mReadOverlapped);
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if(res) { //Operation completed immediately
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DEBUGPRINT("completed, res %i\n", res);
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mWaiting = true;
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} else {
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res = GetLastError();
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if (res == ERROR_IO_PENDING) { //'s ok :)
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DEBUGPRINT("pending\n");
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//WaitCallback will be called
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mWaiting = true;
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} else { //error occurred
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return false;
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}
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}
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return true;
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}
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VOID CALLBACK CEXIETHERNET::ReadWaitCallback(PVOID lpParameter, BOOLEAN TimerFired) {
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VOID CALLBACK CEXIETHERNET::ReadWaitCallback(PVOID lpParameter, BOOLEAN TimerFired)
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{
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static int sNumber = 0;
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int cNumber = sNumber++;
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DEBUGPRINT("WaitCallback %i\n", cNumber);
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if(TimerFired)
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DEBUGPRINT("WaitCallback %i", cNumber);
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if (TimerFired)
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return;
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CEXIETHERNET* self = (CEXIETHERNET*)lpParameter;
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if(self->mHAdapter == INVALID_HANDLE_VALUE)
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return;
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@ -402,33 +429,38 @@ VOID CALLBACK CEXIETHERNET::ReadWaitCallback(PVOID lpParameter, BOOLEAN TimerFir
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&self->mRecvBufferLength, false);
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self->mWaiting = false;
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self->handleRecvdPacket();
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DEBUGPRINT("WaitCallback %i done\n", cNumber);
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DEBUGPRINT("WaitCallback %i done", cNumber);
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}
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union bba_descr {
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union bba_descr
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{
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struct { u32 next_packet_ptr:12, packet_len:12, status:8; };
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u32 word;
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};
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bool CEXIETHERNET::cbwriteDescriptor(u32 size) {
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bool CEXIETHERNET::cbwriteDescriptor(u32 size)
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{
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//if(size < 0x3C) {//60
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#define ETHERNET_HEADER_SIZE 0xE
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if(size < ETHERNET_HEADER_SIZE)
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if (size < ETHERNET_HEADER_SIZE)
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{
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DEBUGPRINT("Packet too small: %i bytes\n", size);
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DEBUGPRINT("Packet too small: %i bytes", size);
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return false;
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}
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size += SIZEOF_RECV_DESCRIPTOR; //The descriptor supposed to include the size of itself
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// The descriptor supposed to include the size of itself
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size += SIZEOF_RECV_DESCRIPTOR;
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//We should probably not implement wraparound here,
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//since neither tmbinc, riptool.dol, or libogc does...
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if(mCbw.p_write() + SIZEOF_RECV_DESCRIPTOR >= CB_SIZE)
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if (mCbw.p_write() + SIZEOF_RECV_DESCRIPTOR >= CB_SIZE)
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{
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DEBUGPRINT("The descriptor won't fit\n");
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DEBUGPRINT("The descriptor won't fit");
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return false;
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}
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if(size >= CB_SIZE)
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if (size >= CB_SIZE)
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{
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DEBUGPRINT("Packet too big: %i bytes\n", size);
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DEBUGPRINT("Packet too big: %i bytes", size);
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return false;
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}
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@ -437,7 +469,7 @@ bool CEXIETHERNET::cbwriteDescriptor(u32 size) {
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descr.packet_len = size;
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descr.status = 0;
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u32 npp;
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if(mCbw.p_write() + size < CB_SIZE)
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if (mCbw.p_write() + size < CB_SIZE)
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{
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npp = mCbw.p_write() + size + CB_OFFSET;
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}
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@ -445,15 +477,19 @@ bool CEXIETHERNET::cbwriteDescriptor(u32 size) {
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{
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npp = mCbw.p_write() + size + CB_OFFSET - CB_SIZE;
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}
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npp = (npp + 0xff) & ~0xff;
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if(npp >= CB_SIZE + CB_OFFSET)
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if (npp >= CB_SIZE + CB_OFFSET)
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npp -= CB_SIZE;
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descr.next_packet_ptr = npp >> 8;
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//DWORD swapped = swapw(descr.word);
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//next_packet_ptr:12, packet_len:12, status:8;
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DEBUGPRINT("Writing descriptor 0x%08X @ 0x%04X: next 0x%03X len 0x%03X status 0x%02X\n",
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DEBUGPRINT("Writing descriptor 0x%08X @ 0x%04X: next 0x%03X len 0x%03X status 0x%02X",
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descr.word, mCbw.p_write() + CB_OFFSET, descr.next_packet_ptr,
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descr.packet_len, descr.status);
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mCbw.write(&descr.word, SIZEOF_RECV_DESCRIPTOR);
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return true;
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@ -23,22 +23,22 @@
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#include "EXI_Device.h"
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#include "EXI_DeviceEthernet.h"
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#define SONICDEBUG
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//#define SONICDEBUG
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#define FILEDEBUG
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#ifdef FILEDEBUG
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FILE *ME = 0;
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#endif
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void DEBUGPRINT (const char * format, ...)
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{
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char buffer[256];
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char buffer[0x1000];
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va_list args;
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va_start (args, format);
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vsprintf (buffer,format, args);
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#ifdef SONICDEBUG
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#ifdef FILEDEBUG
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fprintf(ME, "%s", buffer);
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fprintf(ME, "%s\n", buffer);
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#endif
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printf("%s", buffer);
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printf("%s\n", buffer);
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#else
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INFO_LOG(SP1, buffer);
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#endif
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@ -53,12 +53,7 @@ void DEBUGPRINT (const char * format, ...)
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int mPacketsSent = 0;
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u8 mac_address[6] = {0x00, 0x1A, 0x4D, 0x5E, 0x64, 0x2B}; // Looks Appropriate
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unsigned int Expecting;
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CEXIETHERNET::~CEXIETHERNET()
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{
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#ifdef FILEDEBUG
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fclose(ME);
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#endif
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}
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CEXIETHERNET::CEXIETHERNET() :
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m_uPosition(0),
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m_uCommand(0),
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@ -90,12 +85,21 @@ CEXIETHERNET::CEXIETHERNET() :
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ME = fopen("Debug.txt", "wb");
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#endif
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}
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CEXIETHERNET::~CEXIETHERNET()
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{
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#ifdef FILEDEBUG
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fclose(ME);
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#endif
|
||||
}
|
||||
|
||||
void CyclicBufferWriter::write(void *src, size_t size)
|
||||
{
|
||||
assert(size < _cap);
|
||||
u8* bsrc = (u8*) src;
|
||||
if(_write + size >= _cap)
|
||||
{ //wraparound
|
||||
{
|
||||
// wraparound
|
||||
memcpy(_buffer + _write, src, _cap - _write);
|
||||
memcpy(_buffer, bsrc + (_cap - _write), size - (_cap - _write));
|
||||
_write = size - (_cap - _write);
|
||||
@ -105,17 +109,19 @@ void CyclicBufferWriter::write(void *src, size_t size)
|
||||
memcpy(_buffer + _write, src, size);
|
||||
_write += size;
|
||||
}
|
||||
//DEGUB("CBWrote %i bytes\n", size);
|
||||
//DEGUB("CBWrote %i bytes", size);
|
||||
}
|
||||
|
||||
void CyclicBufferWriter::align()
|
||||
{
|
||||
_write = (_write + 0xff) & ~0xff;
|
||||
if(_write >= _cap)
|
||||
_write -= _cap;
|
||||
}
|
||||
|
||||
void CEXIETHERNET::SetCS(int cs)
|
||||
{
|
||||
DEBUGPRINT("Set CS: %s Expect Variable write?: %s\n", cs ? "true" : "false", mExpectVariableLengthImmWrite ? "true" : "false");
|
||||
DEBUGPRINT("Set CS: %s Expect Variable write?: %s", cs ? "true" : "false", mExpectVariableLengthImmWrite ? "true" : "false");
|
||||
if (!cs)
|
||||
{
|
||||
if (mExpectVariableLengthImmWrite)
|
||||
@ -140,6 +146,7 @@ void CEXIETHERNET::Update()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
bool CEXIETHERNET::IsInterruptSet()
|
||||
{
|
||||
//bool Temp = m_bInterruptSet;
|
||||
@ -154,7 +161,7 @@ void CEXIETHERNET::recordSendComplete()
|
||||
if(mBbaMem[BBA_IMR] & BBA_INTERRUPT_SENT)
|
||||
{
|
||||
mBbaMem[BBA_IR] |= BBA_INTERRUPT_SENT;
|
||||
DEBUGPRINT( "\t\tBBA Send interrupt raised\n");
|
||||
DEBUGPRINT("\t\tBBA Send interrupt raised");
|
||||
//exit(0);
|
||||
m_bInterruptSet = true;
|
||||
//interrupt.raiseEXI("BBA Send");
|
||||
@ -171,13 +178,13 @@ bool CEXIETHERNET::checkRecvBuffer()
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
|
||||
DEBUGPRINT( "IMM Write, size 0x%x, data32: 0x%08x data16: 0x%04x data8: 0x%02x mWriteP 0x%x\n", _uSize, _uData, (u16)Common::swap32(_uData >> 8), (u8)Common::swap32(_uData), mWriteP);
|
||||
DEBUGPRINT("IMM Write, size 0x%x, data32: 0x%08x data16: 0x%04x data8: 0x%02x mWriteP 0x%x", _uSize, _uData, (u16)Common::swap32(_uData >> 8), (u8)Common::swap32(_uData), mWriteP);
|
||||
if (mExpectVariableLengthImmWrite)
|
||||
{
|
||||
DEBUGPRINT("\t[INFO]Variable length IMM write\n");
|
||||
DEBUGPRINT("\t[INFO]Variable length IMM write");
|
||||
if(_uSize == 4)
|
||||
{
|
||||
// Correct
|
||||
@ -195,10 +202,10 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
if (mWriteP + _uSize > BBAMEM_SIZE)
|
||||
{
|
||||
DEBUGPRINT( "[EEE]Write error: mWriteP + size = 0x%04X + %i\n", mWriteP, _uSize);
|
||||
DEBUGPRINT("[EEE]Write error: mWriteP + size = 0x%04X + %i", mWriteP, _uSize);
|
||||
exit(0);
|
||||
}
|
||||
DEBUGPRINT("\t[INFO]Write to BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mWriteP >= CB_OFFSET ? 4 : 2, mWriteP, _uSize, (_uSize==1?"":"s"), _uSize*2, _uData);
|
||||
DEBUGPRINT("\t[INFO]Write to BBA address 0x%0*X, %i byte%s: 0x%0*X",mWriteP >= CB_OFFSET ? 4 : 2, mWriteP, _uSize, (_uSize==1?"":"s"), _uSize*2, _uData);
|
||||
|
||||
switch (mWriteP)
|
||||
{
|
||||
@ -207,33 +214,33 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
// Correct, we use swapped
|
||||
assert(_uSize == 1);
|
||||
u32 SwappedData = Common::swap32(_uData);
|
||||
DEBUGPRINT("\t\t[INFO]BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X\n", mBbaMem[0x09], MAKE(u8, SwappedData), mBbaMem[0x09] & ~MAKE(u8, SwappedData));
|
||||
DEBUGPRINT("\t\t[INFO]BBA Interrupt reset 0x%02X & ~(0x%02X) => 0x%02X", mBbaMem[0x09], MAKE(u8, SwappedData), mBbaMem[0x09] & ~MAKE(u8, SwappedData));
|
||||
mBbaMem[BBA_IR] &= ~MAKE(u8, SwappedData);
|
||||
break;
|
||||
}
|
||||
case BBA_NCRA:
|
||||
{
|
||||
DEBUGPRINT("\t\t[INFO]BBA_NCRA\n");
|
||||
DEBUGPRINT("\t\t[INFO]BBA_NCRA");
|
||||
// Correct, we use the swap here
|
||||
u32 SwappedData = (u8)Common::swap32(_uData);
|
||||
if (RISE(BBA_NCRA_RESET))
|
||||
{
|
||||
// Normal
|
||||
// Whinecube did nothing else as well
|
||||
DEBUGPRINT( "\t\t[INFO]BBA Reset\n");
|
||||
DEBUGPRINT("\t\t[INFO]BBA Reset");
|
||||
}
|
||||
if (RISE(BBA_NCRA_SR) && isActivated())
|
||||
{
|
||||
DEBUGPRINT( "\t\t[INFO]BBA Start Recieve\n");
|
||||
DEBUGPRINT("\t\t[INFO]BBA Start Recieve");
|
||||
//exit(0);
|
||||
startRecv();
|
||||
}
|
||||
if (RISE(BBA_NCRA_ST1))
|
||||
{
|
||||
DEBUGPRINT( "\t\t[INFO]BBA Start Transmit\n");
|
||||
DEBUGPRINT("\t\t[INFO]BBA Start Transmit");
|
||||
if (!mReadyToSend)
|
||||
{
|
||||
DEBUGPRINT( "\t\t\t[EEE]Not ready to send!\n");
|
||||
DEBUGPRINT("\t\t\t[EEE]Not ready to send!");
|
||||
exit(0);
|
||||
//throw hardware_fatal_exception("BBA Transmit without a packet!");
|
||||
}
|
||||
@ -244,7 +251,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
}
|
||||
break;
|
||||
case BBA_NWAYC:
|
||||
DEBUGPRINT( "\t\t[INFO]BBA_NWAYC\n");
|
||||
DEBUGPRINT("\t\t[INFO]BBA_NWAYC");
|
||||
if(Common::swap32(_uData) & (BBA_NWAYC_ANE | BBA_NWAYC_ANS_RA))
|
||||
{
|
||||
//say we've successfully negotiated for 10 Mbit full duplex
|
||||
@ -256,33 +263,33 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
if(_uData != 0x0)
|
||||
{
|
||||
DEBUGPRINT("Not activate!\n");
|
||||
DEBUGPRINT("Not activate!");
|
||||
exit(0);
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
case BBA_RRP: //RRP - Receive Buffer Read Page Pointer
|
||||
DEBUGPRINT( "\t\t[INFO]RRP\n");
|
||||
DEBUGPRINT("\t\t[INFO]RRP");
|
||||
assert(_uSize == 2 || _uSize == 1);
|
||||
mRBRPP = (u8)Common::swap32(_uData) << 8; //Whinecube: I hope this works with both write sizes.
|
||||
mRBEmpty = (mRBRPP == ((u32)mCbw.p_write() + CB_OFFSET));
|
||||
checkRecvBuffer();
|
||||
break;
|
||||
case BBA_RWP: //RWP - Receive Buffer Write Page Pointer
|
||||
DEBUGPRINT( "\t\t[INFO]RWP\n");
|
||||
DEBUGPRINT("\t\t[INFO]RWP");
|
||||
assert(_uSize == 2 || _uSize == 1);
|
||||
DEBUGPRINT("\t\t\tThing is 0x%0X\n", (u32)((u16)mCbw.p_write() + CB_OFFSET) >> 8);
|
||||
DEBUGPRINT("\t\t\tThing is 0x%0X", (u32)((u16)mCbw.p_write() + CB_OFFSET) >> 8);
|
||||
// TODO: This assert FAILS!
|
||||
//assert(Common::swap32(_uData) == (u32)((u16)mCbw.p_write() + CB_OFFSET) >> 8);
|
||||
break;
|
||||
case BBA_NWAYS:
|
||||
DEBUGPRINT("[ERR]Call to BBA_NWAYS directly!\n");
|
||||
DEBUGPRINT("[ERR]Call to BBA_NWAYS directly!");
|
||||
exit(0);
|
||||
break;
|
||||
case BBA_SI_ACTRL2:
|
||||
default:
|
||||
DEBUGPRINT( "\t\t[INFO]Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x\n", _uSize, _uData, Common::swap32(_uData),mWriteP);
|
||||
DEBUGPRINT("\t\t[INFO]Default one!Size 0x%x _uData: 0x%08x Swapped 0x%08x to 0x%x", _uSize, _uData, Common::swap32(_uData),mWriteP);
|
||||
u32 SwappedData = 0;
|
||||
if(_uSize == 4 || _uSize == 1)
|
||||
{
|
||||
@ -291,7 +298,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
SwappedData = Common::swap32(_uData);
|
||||
if(_uSize == 4)
|
||||
{
|
||||
printf("\t\t\tData is 0x%08x\n", SwappedData);
|
||||
DEBUGPRINT("\t\t\tData is 0x%08x", SwappedData);
|
||||
//exit(0);
|
||||
}
|
||||
}
|
||||
@ -299,7 +306,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
//Correct
|
||||
SwappedData = (u16)(_uData >> 16);
|
||||
//printf("\t\t\tData is 0x%04x\n", SwappedData);
|
||||
//DEBUGPRINT("\t\t\tData is 0x%04x", SwappedData);
|
||||
}
|
||||
//u32 SwappedData = _uData;
|
||||
memcpy(mBbaMem + mWriteP, &SwappedData, _uSize);
|
||||
@ -311,7 +318,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
// Device ID Request
|
||||
// 100% this returns correctly
|
||||
DEBUGPRINT( "\t[INFO]Request Dev ID\n");
|
||||
DEBUGPRINT("\t[INFO]Request Dev ID");
|
||||
mSpecialImmData = EXI_DEVTYPE_ETHER;
|
||||
mExpectSpecialImmRead = true;
|
||||
return;
|
||||
@ -319,7 +326,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
else if ((_uSize == 4 && (_uData & 0xC0000000) == 0xC0000000) || (_uSize == 2 && ((u16)Common::swap32(_uData >> 8) & 0x4000) == 0x4000))
|
||||
{
|
||||
// Write to BBA Register
|
||||
DEBUGPRINT( "\t[INFO]Write to BBA register!\n");
|
||||
DEBUGPRINT("\t[INFO]Write to BBA register!");
|
||||
if (_uSize == 4)
|
||||
{
|
||||
// Dunno if this is correct TODO
|
||||
@ -338,11 +345,11 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
{
|
||||
mWriteBuffer.clear();
|
||||
mExpectVariableLengthImmWrite = true;
|
||||
DEBUGPRINT( "\t\t[INFO]Prepared for variable length write to address 0x48\n");
|
||||
DEBUGPRINT("\t\t[INFO]Prepared for variable length write to address 0x48");
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGPRINT( "\t\t[INFO]BBA Write pointer set to 0x%0*X\n", _uSize, mWriteP);
|
||||
DEBUGPRINT("\t\t[INFO]BBA Write pointer set to 0x%0*X", _uSize, mWriteP);
|
||||
//exit(0);
|
||||
}
|
||||
return;
|
||||
@ -358,7 +365,7 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
mReadP = (u16)getbitsw(SwappedData, 8, 23);
|
||||
if (mReadP >= BBAMEM_SIZE)
|
||||
{
|
||||
DEBUGPRINT( "\t\t[EEE]Illegal BBA address: 0x%04X\n", mReadP);
|
||||
DEBUGPRINT("\t\t[EEE]Illegal BBA address: 0x%04X", mReadP);
|
||||
//if(g::bouehr)
|
||||
exit(0);
|
||||
//return EXI_UNHANDLED;
|
||||
@ -370,29 +377,29 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
//size == 2
|
||||
mReadP = (u8)Common::swap32(_uData);
|
||||
}
|
||||
DEBUGPRINT( "\t[INFO]Read from BBA register! 0x%X\n", mReadP);
|
||||
DEBUGPRINT("\t[INFO]Read from BBA register! 0x%X", mReadP);
|
||||
switch (mReadP)
|
||||
{
|
||||
case 0x20: //MAC address
|
||||
DEBUGPRINT( "\t\t[INFO]Mac Address!\n");
|
||||
DEBUGPRINT("\t\t[INFO]Mac Address!");
|
||||
memcpy(mBbaMem + mReadP, mac_address, 6);
|
||||
break;
|
||||
case 0x01: //Revision ID
|
||||
break;
|
||||
case 0x16: //RWP - Receive Buffer Write Page Pointer
|
||||
DEBUGPRINT( "\t\t[INFO]RWP! 0x%04x Swapped 0x%04x\n", (((u16)mCbw.p_write() + CB_OFFSET) >> 8), Common::swap16(((u16)mCbw.p_write() + CB_OFFSET) >> 8));
|
||||
DEBUGPRINT("\t\t[INFO]RWP! 0x%04x Swapped 0x%04x", (((u16)mCbw.p_write() + CB_OFFSET) >> 8), Common::swap16(((u16)mCbw.p_write() + CB_OFFSET) >> 8));
|
||||
//exit(0);
|
||||
// TODO: Dunno if correct
|
||||
MAKE(u16, mBbaMem[mReadP]) = (((u16)mCbw.p_write() + CB_OFFSET) >> 8);
|
||||
break;
|
||||
case 0x18: //RRP - Receive Buffer Read Page Pointer
|
||||
DEBUGPRINT( "\t\t[INFO]RRP!\n");
|
||||
DEBUGPRINT("\t\t[INFO]RRP!");
|
||||
//exit(0);
|
||||
// TODO: Dunno if correct
|
||||
MAKE(u16, mBbaMem[mReadP]) = (mRBRPP) >> 8;
|
||||
break;
|
||||
case 0x3A: //bit 1 set if no data available
|
||||
DEBUGPRINT( "\t\t[INFO]Bit 1 set!\n");
|
||||
DEBUGPRINT("\t\t[INFO]Bit 1 set!");
|
||||
exit(0);
|
||||
//mBbaMem[mReadP] = !mRBEmpty;
|
||||
break;
|
||||
@ -401,12 +408,12 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
//mBbaMem[mReadP] = 0x00;
|
||||
//if(!sendInProgress())
|
||||
mBbaMem[mReadP] &= ~(0x06);
|
||||
//DEBUGPRINT( "\t\t[INFO]mBbaMem[0x%x] &= ~(0x06);! Now 0x%x\n", mReadP, mBbaMem[mReadP]);
|
||||
//DEBUGPRINT("\t\t[INFO]mBbaMem[0x%x] &= ~(0x06);! Now 0x%x", mReadP, mBbaMem[mReadP]);
|
||||
//exit(0);
|
||||
break;
|
||||
case 0x03:
|
||||
mBbaMem[mReadP] = 0x80;
|
||||
//DEBUGPRINT( "\t\t[INFO]mBbaMem[0x%x] = 0x80;! Now %x\n", mReadP, mBbaMem[mReadP]);
|
||||
//DEBUGPRINT("\t\t[INFO]mBbaMem[0x%x] = 0x80;! Now %x", mReadP, mBbaMem[mReadP]);
|
||||
//exit(0);
|
||||
break;
|
||||
case 0x0e:
|
||||
@ -427,25 +434,25 @@ void CEXIETHERNET::ImmWrite(u32 _uData, u32 _uSize)
|
||||
case 0x30: // NWAYC - NWAY Configuration Register
|
||||
break;
|
||||
default:
|
||||
printf("Read from 0x%02x\n", mReadP);
|
||||
DEBUGPRINT("Read from 0x%02x", mReadP);
|
||||
//exit(0);
|
||||
break;
|
||||
}
|
||||
//DEBUGPRINT("BBA Read pointer set to 0x%0*X, Data: 0x%08X\n", _uSize, mReadP, _uData);
|
||||
//DEBUGPRINT("BBA Read pointer set to 0x%0*X, Data: 0x%08X", _uSize, mReadP, _uData);
|
||||
return;
|
||||
}
|
||||
DEBUGPRINT( "\t[EEE]Not expecting ImmWrite of size %d\n", _uSize);
|
||||
DEBUGPRINT( "\t\t[INFO] SKIPPING!\n");
|
||||
DEBUGPRINT("\t[EEE]Not expecting ImmWrite of size %d", _uSize);
|
||||
DEBUGPRINT("\t\t[INFO] SKIPPING!");
|
||||
//exit(0);
|
||||
}
|
||||
|
||||
u32 CEXIETHERNET::ImmRead(u32 _uSize)
|
||||
{
|
||||
DEBUGPRINT( "IMM Read, size 0x%x\n", _uSize);
|
||||
DEBUGPRINT("IMM Read, size 0x%x", _uSize);
|
||||
if (mExpectSpecialImmRead)
|
||||
{
|
||||
// 100% that this returns correctly
|
||||
DEBUGPRINT( "\t[INFO]special IMMRead\n");
|
||||
DEBUGPRINT("\t[INFO]special IMMRead");
|
||||
mExpectSpecialImmRead = false;
|
||||
return mSpecialImmData;
|
||||
}
|
||||
@ -453,7 +460,7 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
|
||||
{
|
||||
if (mReadP + _uSize > BBAMEM_SIZE)
|
||||
{
|
||||
DEBUGPRINT( "\t[EEE]Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize);
|
||||
DEBUGPRINT("\t[EEE]Read error: mReadP + size = 0x%04X + %i", mReadP, _uSize);
|
||||
exit(0);
|
||||
}
|
||||
u32 uResult = 0;
|
||||
@ -461,21 +468,21 @@ u32 CEXIETHERNET::ImmRead(u32 _uSize)
|
||||
// TODO: We do as well?
|
||||
uResult = Common::swap32(uResult); //Whinecube : we have a byteswap problem...
|
||||
|
||||
//DEBUGPRINT("Mem spot is 0x%02x uResult is 0x%x\n", mBbaMem[mReadP], uResult);
|
||||
//DEBUGPRINT("Mem spot is 0x%02x uResult is 0x%x", mBbaMem[mReadP], uResult);
|
||||
/*#ifndef _WIN32
|
||||
if(CheckRecieved())
|
||||
startRecv();
|
||||
#endif*/
|
||||
DEBUGPRINT( "\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X\n",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
|
||||
DEBUGPRINT("\t[INFO]Read from BBA address 0x%0*X, %i byte%s: 0x%0*X",mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize, (_uSize==1?"":"s"),_uSize*2, getbitsw(uResult, 0, _uSize * 8 - 1));
|
||||
mReadP = mReadP + _uSize;
|
||||
return uResult;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGPRINT( "\t[EEE]Unhandled IMM read of %d bytes\n", _uSize);
|
||||
DEBUGPRINT("\t[EEE]Unhandled IMM read of %d bytes", _uSize);
|
||||
exit(0);
|
||||
}
|
||||
DEBUGPRINT( "[EEE]Not Expecting IMMRead of size %d!\n", _uSize);
|
||||
DEBUGPRINT("[EEE]Not Expecting IMMRead of size %d!", _uSize);
|
||||
exit(0);
|
||||
}
|
||||
|
||||
@ -483,13 +490,13 @@ void CEXIETHERNET::DMAWrite(u32 _uAddr, u32 _uSize)
|
||||
{
|
||||
if(mExpectVariableLengthImmWrite)
|
||||
{
|
||||
DEBUGPRINT("DMA Write: Address is 0x%x and size is 0x%x\n", _uAddr, _uSize);
|
||||
DEBUGPRINT("DMA Write: Address is 0x%x and size is 0x%x", _uAddr, _uSize);
|
||||
mWriteBuffer.write(_uSize, Memory::GetPointer(_uAddr));
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGPRINT("Unhandled BBA DMA write: %i, 0x%08X\n", _uSize, _uAddr);
|
||||
DEBUGPRINT("Unhandled BBA DMA write: %i, 0x%08X", _uSize, _uAddr);
|
||||
//if(g::bouehr)
|
||||
exit(0);
|
||||
//return EXI_UNHANDLED;
|
||||
@ -502,12 +509,12 @@ void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize)
|
||||
{
|
||||
if(mReadP + _uSize > BBAMEM_SIZE)
|
||||
{
|
||||
DEBUGPRINT("Read error: mReadP + size = 0x%04X + %i\n", mReadP, _uSize);
|
||||
DEBUGPRINT("Read error: mReadP + size = 0x%04X + %i", mReadP, _uSize);
|
||||
return;
|
||||
}
|
||||
//mem.write_physical(address, size, mBbaMem + mReadP);
|
||||
memcpy(Memory::GetPointer(_uAddr), mBbaMem + mReadP, _uSize);
|
||||
DEBUGPRINT("DMA Read from BBA address 0x%0*X, %i bytes\n",
|
||||
DEBUGPRINT("DMA Read from BBA address 0x%0*X, %i bytes",
|
||||
mReadP >= CB_OFFSET ? 4 : 2, mReadP, _uSize);
|
||||
//exit(0);
|
||||
mReadP = mReadP + _uSize;
|
||||
@ -515,10 +522,10 @@ void CEXIETHERNET::DMARead(u32 _uAddr, u32 _uSize)
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGPRINT("Unhandled BBA DMA read: %i, 0x%08X\n", _uSize, _uAddr);
|
||||
DEBUGPRINT("Unhandled BBA DMA read: %i, 0x%08X", _uSize, _uAddr);
|
||||
//if(g::bouehr)
|
||||
exit(0);
|
||||
//throw bouehr_exception("Unhandled BBA DMA read");
|
||||
//return EXI_UNHANDLED;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
|
||||
#ifndef _EXIDEVICE_ETHERNET_H
|
||||
#define _EXIDEVICE_ETHERNET_H
|
||||
|
||||
#include "Thread.h"
|
||||
|
||||
inline u8 makemaskb(int start, int end) {
|
||||
@ -41,7 +42,8 @@ inline u32 getbitsw(u32 dword, int start, int end) {
|
||||
// Container Class Stolen from Whinecube
|
||||
template<class T> class SubContainer;
|
||||
|
||||
template<class T> class Container {
|
||||
template<class T> class Container
|
||||
{
|
||||
public:
|
||||
Container(size_t _size) {
|
||||
b = 0;
|
||||
@ -53,10 +55,10 @@ public:
|
||||
memcpy(a, data, _size);
|
||||
}
|
||||
~Container() {
|
||||
if(a) /*if(_msize(a))*/ free(a);
|
||||
if (a) /*if(_msize(a))*/ free(a);
|
||||
}
|
||||
void resize(size_t _size) {
|
||||
if(b == _size)
|
||||
if (b == _size)
|
||||
return;
|
||||
free(a);
|
||||
allocate(_size);
|
||||
@ -103,17 +105,20 @@ public:
|
||||
a = other.a; b = other.b;
|
||||
other.a = ta; other.b = tb;
|
||||
}
|
||||
|
||||
protected:
|
||||
void *a;
|
||||
size_t b;
|
||||
|
||||
private:
|
||||
Container(const Container&);
|
||||
Container &operator=(const Container&);
|
||||
Container(void* ptr, size_t _size) : a(ptr), b(_size) {}
|
||||
friend class SubContainer;
|
||||
|
||||
void allocate(size_t _size) {
|
||||
if(_size > (100*1024*1024)) // 100 MB cap
|
||||
void allocate(size_t _size)
|
||||
{
|
||||
if (_size > (100*1024*1024)) // 100 MB cap
|
||||
exit(0);
|
||||
|
||||
//DEGUB("Resize: %i -> %i = %i\n", b, size, g_con_total);
|
||||
@ -122,9 +127,10 @@ private:
|
||||
//}
|
||||
|
||||
b = _size;
|
||||
if(_size == 0)
|
||||
if (_size == 0)
|
||||
a = NULL;
|
||||
else {
|
||||
else
|
||||
{
|
||||
a = malloc(_size);
|
||||
//if(!_CrtIsValidHeapPointer(a))
|
||||
//throw generic_fatal_exception("malloc failed in Container");
|
||||
@ -133,14 +139,21 @@ private:
|
||||
};
|
||||
|
||||
void DEBUGPRINT (const char * format, ...);
|
||||
class WriteBuffer {
|
||||
|
||||
class WriteBuffer
|
||||
{
|
||||
public:
|
||||
WriteBuffer(u32 s) :_size(0) { _buffer = (u8*)malloc(s*sizeof(u8)); ucapacity = s;}
|
||||
WriteBuffer(u32 s) :_size(0)
|
||||
{
|
||||
_buffer = (u8*)malloc(s*sizeof(u8));
|
||||
ucapacity = s;
|
||||
}
|
||||
~WriteBuffer() { free(_buffer);}
|
||||
u32 size() const { return _size; }
|
||||
u32 capacity() const { return ucapacity; }
|
||||
void write(u32 s, const void *src) {
|
||||
if(_size + s >= ucapacity)
|
||||
void write(u32 s, const void *src)
|
||||
{
|
||||
if (_size + s >= ucapacity)
|
||||
{
|
||||
printf("Write too large!");
|
||||
exit(0);
|
||||
@ -149,10 +162,9 @@ public:
|
||||
memcpy(_buffer + _size, src, s);
|
||||
_size = _size + s;
|
||||
}
|
||||
void clear() {
|
||||
_size = 0;
|
||||
}
|
||||
void clear() { _size = 0; }
|
||||
u8* const p() { return _buffer; }
|
||||
|
||||
private:
|
||||
u8* _buffer;
|
||||
u32 ucapacity;
|
||||
@ -162,21 +174,22 @@ private:
|
||||
//Doesn't contain error checks for wraparound writes
|
||||
class CyclicBufferWriter
|
||||
{
|
||||
public:
|
||||
CyclicBufferWriter(u8 *buffer, size_t cap)
|
||||
{
|
||||
_buffer = buffer; _cap = cap; _write = 0;
|
||||
}
|
||||
public:
|
||||
CyclicBufferWriter(u8 *buffer, size_t cap)
|
||||
{
|
||||
_buffer = buffer; _cap = cap; _write = 0;
|
||||
}
|
||||
|
||||
size_t p_write() const { return _write; }
|
||||
void reset() { _write = 0; }
|
||||
size_t p_write() const { return _write; }
|
||||
void reset() { _write = 0; }
|
||||
|
||||
void write(void *src, size_t size);
|
||||
void align(); //aligns the write pointer to steps of 0x100, like the real BBA
|
||||
private:
|
||||
size_t _write;
|
||||
size_t _cap; //capacity
|
||||
u8 *_buffer;
|
||||
void write(void *src, size_t size);
|
||||
void align(); //aligns the write pointer to steps of 0x100, like the real BBA
|
||||
|
||||
private:
|
||||
size_t _write;
|
||||
size_t _cap; //capacity
|
||||
u8 *_buffer;
|
||||
};
|
||||
|
||||
class CEXIETHERNET : public IEXIDevice
|
||||
@ -197,29 +210,30 @@ public:
|
||||
// STATE_TO_SAVE
|
||||
u32 m_uPosition;
|
||||
u32 m_uCommand;
|
||||
|
||||
|
||||
bool m_bInterruptSet;
|
||||
u32 mWriteP, mReadP;
|
||||
#define INVALID_P 0xFFFF
|
||||
|
||||
|
||||
bool mExpectSpecialImmRead; //reset to false on deselect
|
||||
u32 mSpecialImmData;
|
||||
bool Activated;
|
||||
|
||||
|
||||
u16 mRBRPP; //RRP - Receive Buffer Read Page Pointer
|
||||
bool mRBEmpty;
|
||||
|
||||
|
||||
#define BBAMEM_SIZE 0x1000
|
||||
u8 mBbaMem[BBAMEM_SIZE];
|
||||
|
||||
|
||||
WriteBuffer mWriteBuffer;
|
||||
CyclicBufferWriter mCbw;
|
||||
|
||||
|
||||
bool mExpectVariableLengthImmWrite;
|
||||
bool mReadyToSend;
|
||||
unsigned int ID;
|
||||
u8 RegisterBlock[0x1000];
|
||||
enum {
|
||||
enum
|
||||
{
|
||||
CMD_ID = 0x00,
|
||||
CMD_READ_REG = 0x01,
|
||||
};
|
||||
@ -228,7 +242,7 @@ public:
|
||||
bool sendPacket(u8 *etherpckt, int size);
|
||||
bool checkRecvBuffer();
|
||||
bool handleRecvdPacket();
|
||||
|
||||
|
||||
//TAP interface
|
||||
bool activate();
|
||||
bool CheckRecieved();
|
||||
@ -238,7 +252,7 @@ public:
|
||||
bool startRecv();
|
||||
bool cbwriteDescriptor(u32 size);
|
||||
|
||||
|
||||
|
||||
volatile bool mWaiting;
|
||||
Container<u8> mRecvBuffer;
|
||||
#ifdef _WIN32
|
||||
@ -250,73 +264,81 @@ public:
|
||||
#else
|
||||
u32 mRecvBufferLength;
|
||||
#endif
|
||||
};
|
||||
|
||||
};
|
||||
enum {
|
||||
enum
|
||||
{
|
||||
EXPECT_NONE = 0,
|
||||
EXPECT_ID,
|
||||
EXPECT_ID
|
||||
};
|
||||
enum{
|
||||
CB_OFFSET = 0x100,
|
||||
CB_SIZE = (BBAMEM_SIZE - CB_OFFSET),
|
||||
|
||||
// TODO: convert into unions
|
||||
enum
|
||||
{
|
||||
CB_OFFSET = 0x100,
|
||||
CB_SIZE = (BBAMEM_SIZE - CB_OFFSET),
|
||||
SIZEOF_RECV_DESCRIPTOR = 4,
|
||||
|
||||
EXI_DEVTYPE_ETHER = 0x04020200,
|
||||
BBA_NCRA = 0x00, /* Network Control Register A, RW */
|
||||
BBA_NCRA_RESET = (1<<0), /* RESET */
|
||||
BBA_NCRA_ST0 = (1<<1), /* ST0, Start transmit command/status */
|
||||
BBA_NCRA_ST1 = (1<<2), /* ST1, " */
|
||||
BBA_NCRA_SR = (1<<3), /* SR, Start Receive */
|
||||
EXI_DEVTYPE_ETHER = 0x04020200,
|
||||
|
||||
BBA_NCRA = 0x00, // Network Control Register A, RW
|
||||
BBA_NCRA_RESET = 0x01, // RESET
|
||||
BBA_NCRA_ST0 = 0x02, // ST0, Start transmit command/status
|
||||
BBA_NCRA_ST1 = 0x04, // ST1, "
|
||||
BBA_NCRA_SR = 0x08, // SR, Start Receive
|
||||
|
||||
BBA_NCRB = 0x01, /* Network Control Register B, RW */
|
||||
BBA_NCRB_PR = (1<<0), /* PR, Promiscuous Mode */
|
||||
BBA_NCRB_CA = (1<<1), /* CA, Capture Effect Mode */
|
||||
BBA_NCRB_PM = (1<<2), /* PM, Pass Multicast */
|
||||
BBA_NCRB_PB = (1<<3), /* PB, Pass Bad Frame */
|
||||
BBA_NCRB_AB = (1<<4), /* AB, Accept Broadcast */
|
||||
BBA_NCRB_HBD = (1<<5), /* HBD, reserved */
|
||||
BBA_NCRB_RXINTC0 = (1<<6), /* RXINTC, Receive Interrupt Counter */
|
||||
BBA_NCRB_RXINTC1 = (1<<7), /* " */
|
||||
BBA_NCRB_1_PACKET_PER_INT = (0<<6), /* 0 0 */
|
||||
BBA_NCRB_2_PACKETS_PER_INT = (1<<6), /* 0 1 */
|
||||
BBA_NCRB_4_PACKETS_PER_INT = (2<<6), /* 1 0 */
|
||||
BBA_NCRB_8_PACKETS_PER_INT = (3<<6), /* 1 1 */
|
||||
BBA_NCRB = 0x01, // Network Control Register B, RW
|
||||
BBA_NCRB_PR = 0x01, // PR, Promiscuous Mode
|
||||
BBA_NCRB_CA = 0x02, // CA, Capture Effect Mode
|
||||
BBA_NCRB_PM = 0x04, // PM, Pass Multicast
|
||||
BBA_NCRB_PB = 0x08, // PB, Pass Bad Frame
|
||||
BBA_NCRB_AB = 0x10, // AB, Accept Broadcast
|
||||
BBA_NCRB_HBD = 0x20, // HBD, reserved
|
||||
BBA_NCRB_RXINTC0 = 0x40, // RXINTC, Receive Interrupt Counter
|
||||
BBA_NCRB_RXINTC1 = 0x80, // "
|
||||
BBA_NCRB_1_PACKET_PER_INT = 0x00, // 0 0
|
||||
BBA_NCRB_2_PACKETS_PER_INT = 0x40, // 0 1
|
||||
BBA_NCRB_4_PACKETS_PER_INT = 0x80, // 1 0
|
||||
BBA_NCRB_8_PACKETS_PER_INT = 0xC0, // 1 1
|
||||
|
||||
BBA_IMR = 0x08, /* Interrupt Mask Register, RW, 00h */
|
||||
BBA_IMR = 0x08, // Interrupt Mask Register, RW, 00h
|
||||
|
||||
BBA_IR = 0x09, /* Interrupt Register, RW, 00h */
|
||||
BBA_IR_FRAGI = (1<<0), /* FRAGI, Fragment Counter Interrupt */
|
||||
BBA_IR_RI = (1<<1), /* RI, Receive Interrupt */
|
||||
BBA_IR_TI = (1<<2), /* TI, Transmit Interrupt */
|
||||
BBA_IR_REI = (1<<3), /* REI, Receive Error Interrupt */
|
||||
BBA_IR_TEI = (1<<4), /* TEI, Transmit Error Interrupt */
|
||||
BBA_IR_FIFOEI = (1<<5), /* FIFOEI, FIFO Error Interrupt */
|
||||
BBA_IR_BUSEI = (1<<6), /* BUSEI, BUS Error Interrupt */
|
||||
BBA_IR_RBFI = (1<<7), /* RBFI, RX Buffer Full Interrupt */
|
||||
BBA_IR = 0x09, // Interrupt Register, RW, 00h
|
||||
BBA_IR_FRAGI = 0x01, // FRAGI, Fragment Counter Interrupt
|
||||
BBA_IR_RI = 0x02, // RI, Receive Interrupt
|
||||
BBA_IR_TI = 0x04, // TI, Transmit Interrupt
|
||||
BBA_IR_REI = 0x08, // REI, Receive Error Interrupt
|
||||
BBA_IR_TEI = 0x10, // TEI, Transmit Error Interrupt
|
||||
BBA_IR_FIFOEI = 0x20, // FIFOEI, FIFO Error Interrupt
|
||||
BBA_IR_BUSEI = 0x40, // BUSEI, BUS Error Interrupt
|
||||
BBA_IR_RBFI = 0x80, // RBFI, RX Buffer Full Interrupt
|
||||
|
||||
BBA_NWAYC = 0x30, /* NWAY Configuration Register, RW, 84h */
|
||||
BBA_NWAYC_FD = (1<<0), /* FD, Full Duplex Mode */
|
||||
BBA_NWAYC_PS100 = (1<<1), /* PS100/10, Port Select 100/10 */
|
||||
BBA_NWAYC_ANE = (1<<2), /* ANE, Autonegotiation Enable */
|
||||
BBA_NWAYC_ANS_RA = (1<<3), /* ANS, Restart Autonegotiation */
|
||||
BBA_NWAYC_LTE = (1<<7), /* LTE, Link Test Enable */
|
||||
BBA_NWAYC = 0x30, // NWAY Configuration Register, RW, 84h
|
||||
BBA_NWAYC_FD = 0x01, // FD, Full Duplex Mode
|
||||
BBA_NWAYC_PS100 = 0x02, // PS100/10, Port Select 100/10
|
||||
BBA_NWAYC_ANE = 0x04, // ANE, Autonegotiation Enable
|
||||
BBA_NWAYC_ANS_RA = 0x08, // ANS, Restart Autonegotiation
|
||||
BBA_NWAYC_LTE = 0x80, // LTE, Link Test Enable
|
||||
|
||||
BBA_NWAYS = 0x31,
|
||||
BBA_NWAYS_LS10 = (1<<0),
|
||||
BBA_NWAYS_LS100 = (1<<1),
|
||||
BBA_NWAYS_LPNWAY = (1<<2),
|
||||
BBA_NWAYS_ANCLPT = (1<<3),
|
||||
BBA_NWAYS_100TXF = (1<<4),
|
||||
BBA_NWAYS_100TXH = (1<<5),
|
||||
BBA_NWAYS_10TXF = (1<<6),
|
||||
BBA_NWAYS_10TXH = (1<<7),
|
||||
BBA_INTERRUPT_RECV = 0x02,
|
||||
BBA_INTERRUPT_SENT = 0x04,
|
||||
BBA_INTERRUPT_RECV_ERROR = 0x08,
|
||||
BBA_INTERRUPT_SEND_ERROR = 0x10,
|
||||
BBA_RWP = 0x16, /* Receive Buffer Write Page Pointer Register */
|
||||
BBA_RRP = 0x18, /* Receive Buffer Read Page Pointer Register */
|
||||
BBA_SI_ACTRL2 = 0x60,
|
||||
BBA_NWAYS = 0x31,
|
||||
BBA_NWAYS_LS10 = 0x01,
|
||||
BBA_NWAYS_LS100 = 0x02,
|
||||
BBA_NWAYS_LPNWAY = 0x04,
|
||||
BBA_NWAYS_ANCLPT = 0x08,
|
||||
BBA_NWAYS_100TXF = 0x10,
|
||||
BBA_NWAYS_100TXH = 0x20,
|
||||
BBA_NWAYS_10TXF = 0x40,
|
||||
BBA_NWAYS_10TXH = 0x80,
|
||||
|
||||
BBA_INTERRUPT_RECV = 0x02,
|
||||
BBA_INTERRUPT_SENT = 0x04,
|
||||
BBA_INTERRUPT_RECV_ERROR = 0x08,
|
||||
BBA_INTERRUPT_SEND_ERROR = 0x10,
|
||||
|
||||
BBA_RWP = 0x16, // Receive Buffer Write Page Pointer Register
|
||||
BBA_RRP = 0x18, // Receive Buffer Read Page Pointer Register
|
||||
|
||||
BBA_SI_ACTRL2 = 0x60
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@ -626,14 +626,16 @@ Global
|
||||
{823DDC98-42D5-4A38-88CF-9DC06C788AE4}.Release|x64.Build.0 = Release|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Debug|x64.ActiveCfg = Debug|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Debug|x64.ActiveCfg = Debug|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Debug|x64.Build.0 = Debug|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|Win32.ActiveCfg = Debug|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|Win32.Build.0 = Debug|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|x64.ActiveCfg = DebugFast|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|x64.Build.0 = DebugFast|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|x64.ActiveCfg = Debug|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.DebugFast|x64.Build.0 = Debug|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release_JITIL|Win32.ActiveCfg = Release|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release_JITIL|Win32.Build.0 = Release|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release_JITIL|x64.ActiveCfg = Release|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release_JITIL|x64.ActiveCfg = Release|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release_JITIL|x64.Build.0 = Release|x64
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release|Win32.Build.0 = Release|Win32
|
||||
{40C636FA-B5BF-4D67-ABC8-376B524A7551}.Release|x64.ActiveCfg = Release|x64
|
||||
|
||||
Loading…
Reference in New Issue
Block a user