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JitRegCache: Add IsZero to RCOpArg
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@ -56,6 +56,7 @@ public:
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bool IsImm() const;
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bool IsImm() const;
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s32 SImm32() const;
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s32 SImm32() const;
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u32 Imm32() const;
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u32 Imm32() const;
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bool IsZero() const { return IsImm() && Imm32() == 0; }
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private:
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private:
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friend class RegCache;
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friend class RegCache;
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