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Merge pull request #210 from magumagu/writerex-fix
Fix OpArg::WriteRex with 8-bit memory operand.
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commit
5fc6ce59c3
@ -126,32 +126,34 @@ void OpArg::WriteRex(XEmitter *emit, int opBits, int bits, int customOp) const
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if (customOp == -1) customOp = operandReg;
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#if _M_X86_64
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u8 op = 0x40;
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// REX.W (whether operation is a 64-bit operation)
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if (opBits == 64) op |= 8;
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// REX.R (whether ModR/M reg field refers to R8-R15.
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if (customOp & 8) op |= 4;
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// REX.X (whether ModR/M SIB index field refers to R8-R15)
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if (indexReg & 8) op |= 2;
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if (offsetOrBaseReg & 8) op |= 1; //TODO investigate if this is dangerous
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// REX.B (whether ModR/M rm or SIB base or opcode reg field refers to R8-R15)
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if (offsetOrBaseReg & 8) op |= 1;
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// Write REX if wr have REX bits to write, or if the operation accesses
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// SIL, DIL, BPL, or SPL.
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if (op != 0x40 ||
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(bits == 8 && (offsetOrBaseReg & 0x10c) == 4) ||
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(scale == SCALE_NONE && bits == 8 && (offsetOrBaseReg & 0x10c) == 4) ||
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(opBits == 8 && (customOp & 0x10c) == 4)) {
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emit->Write8(op);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0 || bits != 8);
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_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0 || opBits != 8);
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} else {
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x10c) == 0 ||
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(offsetOrBaseReg & 0x10c) == 0x104 ||
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bits != 8);
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_dbg_assert_(DYNA_REC, (customOp & 0x10c) == 0 ||
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(customOp & 0x10c) == 0x104 ||
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opBits != 8);
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// Check the operation doesn't access AH, BH, CH, or DH.
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0);
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_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0);
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}
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#else
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// Make sure we don't perform a 64-bit operation.
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_dbg_assert_(DYNA_REC, opBits != 64);
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_dbg_assert_(DYNA_REC, (customOp & 8) == 0 || customOp == -1);
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// Make sure the operation doesn't access R8-R15 registers.
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_dbg_assert_(DYNA_REC, (customOp & 8) == 0);
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_dbg_assert_(DYNA_REC, (indexReg & 8) == 0);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 8) == 0);
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_dbg_assert_(DYNA_REC, opBits != 8 || (customOp & 0x10c) != 4 || customOp == -1);
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_dbg_assert_(DYNA_REC, bits != 8 || (offsetOrBaseReg & 0x10c) != 4);
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// Make sure the operation doesn't access SIL, DIL, BPL, or SPL.
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_dbg_assert_(DYNA_REC, opBits != 8 || (customOp & 0x10c) != 4);
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_dbg_assert_(DYNA_REC, scale != SCALE_NONE || bits != 8 || (offsetOrBaseReg & 0x10c) != 4);
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#endif
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}
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