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JIT: various float optimizations
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parent
34287b8042
commit
7b0f559ae1
@ -10,8 +10,8 @@
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using namespace Gen;
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static const u64 GC_ALIGNED16(psSignBits2[2]) = {0x8000000000000000ULL, 0x8000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask2[2]) = {0x7FFFFFFFFFFFFFFFULL, 0x7FFFFFFFFFFFFFFFULL};
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static const u64 GC_ALIGNED16(psSignBits2[2]) = {0x8000000000000000ULL, 0x0000000000000000ULL};
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static const u64 GC_ALIGNED16(psAbsMask2[2]) = {0x7FFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL};
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static const double GC_ALIGNED16(half_qnan_and_s32_max[2]) = {0x7FFFFFFF, -0x80000};
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void Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (XEmitter::*op)(Gen::X64Reg, Gen::OpArg), UGeckoInstruction inst, bool roundRHS)
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@ -77,16 +77,7 @@ void Jit64::fp_tri_op(int d, int a, int b, bool reversible, bool single, void (X
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if (single)
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{
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ForceSinglePrecisionS(fpr.RX(d));
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if (cpu_info.bSSE3)
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{
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MOVDDUP(fpr.RX(d), fpr.R(d));
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}
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else
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{
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if (!fpr.R(d).IsSimpleReg(fpr.RX(d)))
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MOVQ_xmm(fpr.RX(d), fpr.R(d));
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UNPCKLPD(fpr.RX(d), R(fpr.RX(d)));
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}
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MOVDDUP(fpr.RX(d), fpr.R(d));
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}
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SetFPRFIfNeeded(inst, fpr.RX(d));
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fpr.UnlockAll();
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@ -136,29 +127,29 @@ void Jit64::fmaddXX(UGeckoInstruction inst)
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int d = inst.FD;
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fpr.Lock(a, b, c, d);
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MOVSD(XMM0, fpr.R(c));
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if (single_precision)
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Force25BitPrecision(XMM0, XMM1);
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switch (inst.SUBOP5)
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// nmsub is implemented a little differently ((b - a*c) instead of -(a*c - b)), so handle it separately
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if (inst.SUBOP5 == 30) //nmsub
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{
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case 28: //msub
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MOVSD(XMM1, fpr.R(c));
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if (single_precision)
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Force25BitPrecision(XMM1, XMM0);
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MULSD(XMM1, fpr.R(a));
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MOVSD(XMM0, fpr.R(b));
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SUBSD(XMM0, R(XMM1));
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}
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else
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{
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MOVSD(XMM0, fpr.R(c));
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if (single_precision)
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Force25BitPrecision(XMM0, XMM1);
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MULSD(XMM0, fpr.R(a));
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SUBSD(XMM0, fpr.R(b));
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break;
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case 29: //madd
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MULSD(XMM0, fpr.R(a));
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ADDSD(XMM0, fpr.R(b));
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break;
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case 30: //nmsub
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MULSD(XMM0, fpr.R(a));
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SUBSD(XMM0, fpr.R(b));
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PXOR(XMM0, M((void*)&psSignBits2));
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break;
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case 31: //nmadd
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MULSD(XMM0, fpr.R(a));
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ADDSD(XMM0, fpr.R(b));
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PXOR(XMM0, M((void*)&psSignBits2));
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break;
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if (inst.SUBOP5 == 28) //msub
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SUBSD(XMM0, fpr.R(b));
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else //(n)madd
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ADDSD(XMM0, fpr.R(b));
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if (inst.SUBOP5 == 31) //nmadd
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PXOR(XMM0, M((void*)&psSignBits2));
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}
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fpr.BindToRegister(d, false);
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//YES it is necessary to dupe the result :(
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@ -186,23 +177,26 @@ void Jit64::fsign(UGeckoInstruction inst)
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int b = inst.FB;
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fpr.Lock(b, d);
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fpr.BindToRegister(d, true, true);
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MOVSD(XMM0, fpr.R(b));
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if (d != b)
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MOVSD(fpr.RX(d), fpr.R(b));
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switch (inst.SUBOP10)
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{
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case 40: // fnegx
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PXOR(XMM0, M((void*)&psSignBits2));
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// We can cheat and not worry about clobbering the top half by using masks
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// that don't modify the top half.
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PXOR(fpr.RX(d), M((void*)&psSignBits2));
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break;
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case 264: // fabsx
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PAND(XMM0, M((void*)&psAbsMask2));
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PAND(fpr.RX(d), M((void*)&psAbsMask2));
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break;
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case 136: // fnabs
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POR(XMM0, M((void*)&psSignBits2));
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POR(fpr.RX(d), M((void*)&psSignBits2));
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break;
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default:
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PanicAlert("fsign bleh");
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break;
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}
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MOVSD(fpr.R(d), XMM0);
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fpr.UnlockAll();
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}
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@ -220,14 +214,22 @@ void Jit64::fmrx(UGeckoInstruction inst)
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fpr.Lock(b, d);
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// We don't need to load d, but if it is loaded, we need to mark it as dirty.
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if (fpr.IsBound(d))
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{
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// We don't need to load d, but if it is loaded, we need to mark it as dirty.
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fpr.BindToRegister(d);
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// b needs to be in a register because "MOVSD reg, mem" sets the upper bits (64+) to zero and we don't want that.
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fpr.BindToRegister(b, true, false);
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MOVSD(fpr.R(d), fpr.RX(b));
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// We have to use MOVLPD if b isn't loaded because "MOVSD reg, mem" sets the upper bits (64+)
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// to zero and we don't want that.
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if (!fpr.R(b).IsSimpleReg())
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MOVLPD(fpr.RX(d), fpr.R(b));
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else
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MOVSD(fpr.R(d), fpr.RX(b));
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}
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else
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{
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fpr.BindToRegister(b, true, false);
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MOVSD(fpr.R(d), fpr.RX(b));
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}
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fpr.UnlockAll();
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}
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