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DSP tests: update DSP MMIO labels

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This commit is contained in:
Tillmann Karras
2025-04-24 13:45:55 +01:00
parent 6c870860ea
commit 7c7c179b44
7 changed files with 40 additions and 40 deletions
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8
Source/Core/Core/DSP/DSPTables.cpp
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@ -400,7 +400,7 @@ const std::array<pdlabel_t, 96> pdlabels =
{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
{0xffd0, "0xffd0",nullptr,},
{0xffd1, "SampleFormat", "SampleFormat",},
{0xffd1, "FORMAT", "Accelerator sample format",},
{0xffd2, "0xffd2",nullptr,},
{0xffd3, "ACDRAW", "Accelerator raw read/write from ARAM",},
{0xffd4, "ACSAH", "Accelerator start address H",},
@ -409,9 +409,9 @@ const std::array<pdlabel_t, 96> pdlabels =
{0xffd7, "ACEAL", "Accelerator end address L",},
{0xffd8, "ACCAH", "Accelerator current address H",},
{0xffd9, "ACCAL", "Accelerator current address L",},
{0xffda, "pred_scale", "pred_scale",},
{0xffdb, "yn1", "yn1",},
{0xffdc, "yn2", "yn2",},
{0xffda, "PRED_SCALE", "ADPCM predictor and scale",},
{0xffdb, "YN1", "ADPCM output history Y[N - 1]",},
{0xffdc, "YN2", "ADPCM output history Y[N - 2]",},
{0xffdd, "ACDSAMP", "Accelerator processed sample read from ARAM or ACIN",},
{0xffde, "GAIN", "Gain",},
{0xffdf, "ACIN", "Accelerator MMIO PCM input value",},

18
Source/DSPSpy/tests/accelerator_loop_test.ds
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@ -11,7 +11,7 @@ lri $AC1.L, #0x0011 ; end
; Set the sample format
lri $AC0.H, #0x0
sr @0xffd1, $AC0.H
sr @FORMAT, $AC0.H
; Set the starting and current address
srs @ACSAH, $AC0.M
srs @ACCAH, $AC0.M
@ -23,9 +23,9 @@ srs @ACEAL, $AC1.L
; Reset some registers (these must be reset after setting FORMAT)
lri $AC0.H, #0xffff
sr @0xffda, $AC0.H ; pred scale
sr @0xffdb, $AC0.H ; yn1
sr @0xffdc, $AC0.H ; yn2
sr @PRED_SCALE, $AC0.H
sr @YN1, $AC0.H
sr @YN2, $AC0.H
call load_hw_reg_to_regs
call send_back ; check the accelerator regs before a read
@ -41,12 +41,12 @@ end_of_loop:
jmp end_of_test
load_hw_reg_to_regs:
lr $AR0, @0xffd1 ; format
lr $AR0, @FORMAT
lr $AR1, @0xffd2 ; unknown
lr $AR2, @0xffda ; pred scale
lr $AR3, @0xffdb ; yn1
lr $IX0, @0xffdc ; yn2
lr $IX1, @0xffdf ; unknown accelerator register
lr $AR2, @PRED_SCALE
lr $AR3, @YN1
lr $IX0, @YN2
lr $IX1, @ACIN
lri $AC0.H, #0
lrs $AC0.M, @ACSAH

18
Source/DSPSpy/tests/accelerator_pcm_test.ds
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@ -11,7 +11,7 @@ lri $AC1.L, #0x0011 ; end
; Set the sample format
lri $AC0.H, #0x08 ; 4-bit PCM, gain scaling = x / 2048
sr @0xffd1, $AC0.H
sr @FORMAT, $AC0.H
; Set the starting and current address
srs @ACSAH, $AC0.M
srs @ACCAH, $AC0.M
@ -28,9 +28,9 @@ si @COEF_A2_0, #0x0200 ; 512 / 2048 = 0.25
; Reset some registers (these must be reset after setting FORMAT)
lri $AC0.H, #0x0000
sr @0xffda, $AC0.H ; pred scale, use 0th coefficients
sr @0xffdb, $AC0.H ; yn1
sr @0xffdc, $AC0.H ; yn2
sr @PRED_SCALE, $AC0.H ; use 0th coefficients
sr @YN1, $AC0.H
sr @YN2, $AC0.H
call load_hw_reg_to_regs
call send_back ; check the accelerator regs before a read
@ -53,12 +53,12 @@ end_of_loop:
jmp end_of_test
load_hw_reg_to_regs:
lr $AR0, @0xffd1 ; format
lr $AR0, @FORMAT
lr $AR1, @0xffd2 ; unknown
lr $AR2, @0xffda ; pred scale
lr $AR3, @0xffdb ; yn1
lr $IX0, @0xffdc ; yn2
lr $IX1, @0xffdf ; unknown accelerator register
lr $AR2, @PRED_SCALE
lr $AR3, @YN1
lr $IX0, @YN2
lr $IX1, @ACIN
lri $AC0.H, #0
lrs $AC0.M, @ACSAH

14
Source/DSPSpy/tests/accelerator_raw_test.ds
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@ -6,7 +6,7 @@ include "dsp_base.inc"
; and verify things look correct
loop_read_test:
; Set the sample format
sr @0xffd1, $AC0.H
sr @FORMAT, $AC0.H
; Test parameters
lri $AC0.M, #0x0000 ; start
@ -39,7 +39,7 @@ end_of_read_loop:
loop_write_test:
; Set the sample format
sr @0xffd1, $AC0.H
sr @FORMAT, $AC0.H
; Test parameters
lri $AC0.M, #0x0000 ; start
@ -86,12 +86,12 @@ call loop_write_test
jmp end_of_test
load_hw_reg_to_regs:
lr $AR0, @0xffd1 ; format
lr $AR0, @FORMAT
lr $AR1, @0xffd2 ; unknown
lr $AR2, @0xffda ; pred scale
lr $AR3, @0xffdb ; yn1
lr $IX0, @0xffdc ; yn2
lr $IX1, @0xffdf ; unknown accelerator register
lr $AR2, @PRED_SCALE
lr $AR3, @YN1
lr $IX0, @YN2
lr $IX1, @ACIN
lri $AC0.H, #0
lrs $AC0.M, @ACSAH

2
Source/DSPSpy/tests/accelerator_test.ds
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@ -12,7 +12,7 @@ include "dsp_base.inc"
; AC1.M/L: end address
test_accelerator_addrs_ex:
; Set the sample format
sr @0xffd1, $AC0.H
sr @FORMAT, $AC0.H
; Set the accelerator start and current address.
srs @ACSAH, $AC0.M

6
Source/DSPSpy/tests/dsp_base_noirq.inc
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@ -142,10 +142,10 @@ irq5:
si @DMBL, #0x0000
si @DIRQ, #0x0001
lri $ac0.m, #0xbbbb
sr @0xffda, $ac0.m ; pred scale
sr @0xffdb, $ac0.m ; yn1
sr @PRED_SCALE, $ac0.m
sr @YN1, $ac0.m
lr $ix2, @ACDSAMP
sr @0xffdc, $ac0.m ; yn2
sr @YN2, $ac0.m
rti
irq6:
lri $ac0.m, #0x0006

14
Source/DSPSpy/tests/rti_test.ds
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@ -14,10 +14,10 @@ include "dsp_base_noirq.inc"
test_main:
; Use the accelerator to generate an IRQ by setting the start and end address to 0
; This will result in an interrupt on every read
SI @0xffda, #0 ; pred_scale
SI @0xffdb, #0 ; yn1
SI @0xffdc, #0 ; yn2
SI @0xffd1, #0 ; SampleFormat
SI @PRED_SCALE, #0
SI @YN1, #0
SI @YN2, #0
SI @FORMAT, #0
SI @ACSAH, #0
SI @ACCAH, #0
SI @ACSAL, #0
@ -42,9 +42,9 @@ test_main:
accov_irq:
; Restore registers, otherwise no new interrupt will be generated
SI @0xffda, #0 ; pred_scale
SI @0xffdb, #0 ; yn1
SI @0xffdc, #0 ; yn2
SI @PRED_SCALE, #0
SI @YN1, #0
SI @YN2, #0
TSTAXH $AX1.H
LRI $AX1.L, #0x1111