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Jit64: Optimize dcbx being called in a loop over a large memory region.
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@ -234,20 +234,94 @@ void Jit64::dcbx(UGeckoInstruction inst)
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INSTRUCTION_START
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JITDISABLE(bJITLoadStoreOff);
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X64Reg addr = RSCRATCH;
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X64Reg value = RSCRATCH2;
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// Check if the next instructions match a known looping pattern:
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// - dcbx rX
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// - addi rX,rX,32
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// - bdnz+ -8
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const bool make_loop = inst.RA == 0 && inst.RB != 0 && CanMergeNextInstructions(2) &&
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(js.op[1].inst.hex & 0xfc00'ffff) == 0x38000020 &&
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js.op[1].inst.RA_6 == inst.RB && js.op[1].inst.RD_2 == inst.RB &&
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js.op[2].inst.hex == 0x4200fff8;
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RCOpArg Ra = inst.RA ? gpr.Use(inst.RA, RCMode::Read) : RCOpArg::Imm32(0);
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RCOpArg Rb = gpr.Use(inst.RB, RCMode::Read);
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RCX64Reg Rb = gpr.Bind(inst.RB, make_loop ? RCMode::ReadWrite : RCMode::Read);
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RCX64Reg tmp = gpr.Scratch();
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RCX64Reg effective_address = gpr.Scratch();
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RegCache::Realize(Ra, Rb, tmp, effective_address);
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// Translate effective address to physical address.
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RCX64Reg loop_counter;
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if (make_loop)
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{
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// We'll execute somewhere between one single cacheline invalidation and however many are needed
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// to reduce the downcount to zero, never exceeding the amount requested by the game.
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// To stay consistent with the rest of the code we adjust the involved registers (CTR and Rb)
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// by the amount of cache lines we invalidate minus one -- since we'll run the regular addi and
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// bdnz afterwards! So if we invalidate a single cache line, we don't adjust the registers at
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// all, if we invalidate 2 cachelines we adjust the registers by one step, and so on.
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RCX64Reg& reg_cycle_count = tmp;
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RCX64Reg& reg_downcount = effective_address;
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loop_counter = gpr.Scratch();
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RegCache::Realize(loop_counter);
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// This must be true in order for us to pick up the DIV results and not trash any data.
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static_assert(RSCRATCH == Gen::EAX && RSCRATCH2 == Gen::EDX);
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// Alright, now figure out how many loops we want to do.
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const u8 cycle_count_per_loop =
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js.op[0].opinfo->numCycles + js.op[1].opinfo->numCycles + js.op[2].opinfo->numCycles;
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// This is both setting the adjusted loop count to 0 for the downcount <= 0 case and clearing
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// the upper bits for the DIV instruction in the downcount > 0 case.
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XOR(32, R(RSCRATCH2), R(RSCRATCH2));
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MOV(32, R(reg_downcount), PPCSTATE(downcount));
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TEST(32, R(reg_downcount), R(reg_downcount)); // if (downcount <= 0)
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FixupBranch downcount_is_zero_or_negative = J_CC(CC_LE); // only do 1 invalidation; else:
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MOV(32, R(loop_counter), PPCSTATE_CTR);
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MOV(32, R(RSCRATCH), R(reg_downcount));
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MOV(32, R(reg_cycle_count), Imm32(cycle_count_per_loop));
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DIV(32, R(reg_cycle_count)); // RSCRATCH = downcount / cycle_count
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LEA(32, RSCRATCH2, MDisp(loop_counter, -1)); // RSCRATCH2 = CTR - 1
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// ^ Note that this CTR-1 implicitly handles the CTR == 0 case correctly.
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CMP(32, R(RSCRATCH), R(RSCRATCH2));
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CMOVcc(32, RSCRATCH2, R(RSCRATCH), CC_B); // RSCRATCH2 = min(RSCRATCH, RSCRATCH2)
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// RSCRATCH2 now holds the amount of loops to execute minus 1, which is the amount we need to
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// adjust downcount, CTR, and Rb by to exit the loop construct with the right values in those
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// registers.
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SUB(32, R(loop_counter), R(RSCRATCH2));
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MOV(32, PPCSTATE_CTR, R(loop_counter)); // CTR -= RSCRATCH2
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MOV(32, R(RSCRATCH), R(RSCRATCH2));
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IMUL(32, RSCRATCH, R(reg_cycle_count));
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// ^ Note that this cannot overflow because it's limited by (downcount/cycle_count).
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SUB(32, R(reg_downcount), R(RSCRATCH));
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MOV(32, PPCSTATE(downcount), R(reg_downcount)); // downcount -= (RSCRATCH2 * reg_cycle_count)
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SetJumpTarget(downcount_is_zero_or_negative);
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// Load the loop_counter register with the amount of invalidations to execute.
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LEA(32, loop_counter, MDisp(RSCRATCH2, 1));
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}
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X64Reg value = RSCRATCH;
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MOV_sum(32, value, Ra, Rb);
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if (make_loop)
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{
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// This is the best place to adjust Rb to what it should be since RSCRATCH2 still has the
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// adjusted loop count and we're done reading from Rb.
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SHL(32, R(RSCRATCH2), Imm8(5));
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ADD(32, R(Rb), R(RSCRATCH2)); // Rb += (RSCRATCH2 * 32)
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}
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X64Reg addr = RSCRATCH2;
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FixupBranch bat_lookup_failed;
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MOV(32, R(effective_address), R(value));
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const u8* loop_start = GetCodePtr();
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if (MSR.IR)
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{
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// Translate effective address to physical address.
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bat_lookup_failed = BATAddressLookup(value, tmp, PowerPC::ibat_table.data());
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MOV(32, R(addr), R(effective_address));
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AND(32, R(addr), Imm32(0x0001ffff));
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@ -264,6 +338,14 @@ void Jit64::dcbx(UGeckoInstruction inst)
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BT(32, R(value), R(addr));
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FixupBranch invalidate_needed = J_CC(CC_C, true);
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if (make_loop)
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{
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ADD(32, R(effective_address), Imm8(32));
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MOV(32, R(value), R(effective_address));
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SUB(32, R(loop_counter), Imm8(1));
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J_CC(CC_NZ, loop_start);
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}
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SwitchToFarCode();
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SetJumpTarget(invalidate_needed);
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if (MSR.IR)
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@ -272,9 +354,20 @@ void Jit64::dcbx(UGeckoInstruction inst)
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BitSet32 registersInUse = CallerSavedRegistersInUse();
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registersInUse[X64Reg(tmp)] = false;
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registersInUse[X64Reg(effective_address)] = false;
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if (make_loop)
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registersInUse[X64Reg(loop_counter)] = false;
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ABI_PushRegistersAndAdjustStack(registersInUse, 0);
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MOV(32, R(ABI_PARAM1), R(effective_address));
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ABI_CallFunction(JitInterface::InvalidateICacheLine);
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if (make_loop)
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{
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MOV(32, R(ABI_PARAM1), R(effective_address));
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MOV(32, R(ABI_PARAM2), R(loop_counter));
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ABI_CallFunction(JitInterface::InvalidateICacheLines);
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}
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else
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{
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MOV(32, R(ABI_PARAM1), R(effective_address));
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ABI_CallFunction(JitInterface::InvalidateICacheLine);
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}
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ABI_PopRegistersAndAdjustStack(registersInUse, 0);
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asm_routines.ResetStack(*this);
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@ -230,6 +230,22 @@ void InvalidateICacheLine(u32 address)
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g_jit->GetBlockCache()->InvalidateICacheLine(address);
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}
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void InvalidateICacheLines(u32 address, u32 count)
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{
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// This corresponds to a PPC code loop that:
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// - calls some form of dcb* instruction on 'address'
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// - increments 'address' by the size of a cache line (0x20 bytes)
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// - decrements 'count' by 1
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// - jumps back to the dcb* instruction if 'count' != 0
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// with an extra optimization for the case of a single cache line invalidation
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if (count == 1)
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InvalidateICacheLine(address);
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if (count == 0 || count >= static_cast<u32>(0x1'0000'0000 / 32))
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InvalidateICache(address & ~0x1f, 0xffffffff, false);
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else
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InvalidateICache(address & ~0x1f, 32 * count, false);
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}
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void CompileExceptionCheck(ExceptionType type)
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{
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if (!g_jit)
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@ -63,6 +63,7 @@ void ClearSafe();
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// If "forced" is true, a recompile is being requested on code that hasn't been modified.
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void InvalidateICache(u32 address, u32 size, bool forced);
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void InvalidateICacheLine(u32 address);
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void InvalidateICacheLines(u32 address, u32 count);
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void CompileExceptionCheck(ExceptionType type);
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