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Merge pull request #9810 from JosJuice/fprf-cmp-mask

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Jits: Fix fcmpX FPRF mask
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Tilka 2021-06-27 19:32:19 +01:00 committed by GitHub
commit aff39af5fb
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4 changed files with 6 additions and 4 deletions
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1
Source/Core/Core/PowerPC/Gekko.h
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@ -401,6 +401,7 @@ union UReg_MSR
#define FPRF_SHIFT 12
#define FPRF_WIDTH 5
#define FPRF_MASK (0x1F << FPRF_SHIFT)
#define FPCC_MASK (0xF << FPRF_SHIFT)
// FPSCR exception flags
enum FPSCRExceptionFlag : u32

5
Source/Core/Core/PowerPC/Interpreter/Interpreter_FloatingPoint.cpp
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@ -7,6 +7,7 @@
#include "Common/CommonTypes.h"
#include "Common/FloatUtils.h"
#include "Core/PowerPC/Gekko.h"
#include "Core/PowerPC/Interpreter/Interpreter.h"
#include "Core/PowerPC/Interpreter/Interpreter_FPUtils.h"
#include "Core/PowerPC/PowerPC.h"
@ -169,7 +170,7 @@ void Interpreter::Helper_FloatCompareOrdered(UGeckoInstruction inst, double fa,
const u32 compare_value = static_cast<u32>(compare_result);
// Clear and set the FPCC bits accordingly.
FPSCR.FPRF = (FPSCR.FPRF & ~0xF) | compare_value;
FPSCR.FPRF = (FPSCR.FPRF & ~FPCC_MASK) | compare_value;
PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
}
@ -203,7 +204,7 @@ void Interpreter::Helper_FloatCompareUnordered(UGeckoInstruction inst, double fa
const u32 compare_value = static_cast<u32>(compare_result);
// Clear and set the FPCC bits accordingly.
FPSCR.FPRF = (FPSCR.FPRF & ~0xF) | compare_value;
FPSCR.FPRF = (FPSCR.FPRF & ~FPCC_MASK) | compare_value;
PowerPC::ppcState.cr.SetField(inst.CRFD, compare_value);
}

2
Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp
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@ -631,7 +631,7 @@ void Jit64::FloatCompare(UGeckoInstruction inst, bool upper)
RegCache::Realize(Ra, Rb);
if (fprf)
AND(32, PPCSTATE(fpscr), Imm32(~FPRF_MASK));
AND(32, PPCSTATE(fpscr), Imm32(~FPCC_MASK));
if (upper)
{

2
Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp
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@ -402,7 +402,7 @@ void JitArm64::fcmpX(UGeckoInstruction inst)
{
fpscr_reg = gpr.GetReg();
LDR(IndexType::Unsigned, fpscr_reg, PPC_REG, PPCSTATE_OFF(fpscr));
ANDI2R(fpscr_reg, fpscr_reg, ~FPRF_MASK);
ANDI2R(fpscr_reg, fpscr_reg, ~FPCC_MASK);
}
FixupBranch pNaN, pLesser, pGreater;