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x64EmitterTest: Add some missing tests
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@ -882,9 +882,27 @@ TWO_OP_SSE_TEST(PMOVZXWD, "qword")
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TWO_OP_SSE_TEST(PMOVZXWQ, "dword")
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TWO_OP_SSE_TEST(PMOVZXDQ, "qword")
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// TODO: BLEND
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TWO_OP_SSE_TEST(PBLENDVB, "dqword")
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TWO_OP_SSE_TEST(BLENDVPS, "dqword")
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TWO_OP_SSE_TEST(BLENDVPD, "dqword")
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// TODO: AVX
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#define TWO_OP_PLUS_IMM_SSE_TEST(Name, MemBits) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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for (const auto& r1 : xmmnames) \
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{ \
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for (const auto& r2 : xmmnames) \
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{ \
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emitter->Name(r1.reg, R(r2.reg), 0x0b); \
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ExpectDisassembly(#Name " " + r1.name + ", " + r2.name + ", 0x0b"); \
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} \
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emitter->Name(r1.reg, MatR(R12), 0x0b); \
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ExpectDisassembly(#Name " " + r1.name + ", " MemBits " ptr ds:[r12], 0x0b"); \
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} \
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}
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TWO_OP_PLUS_IMM_SSE_TEST(BLENDPS, "dqword")
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TWO_OP_PLUS_IMM_SSE_TEST(BLENDPD, "dqword")
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// for VEX GPR instructions that take the form op reg, r/m, reg
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#define VEX_RMR_TEST(Name) \
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@ -1035,6 +1053,26 @@ VEX_RMI_TEST(RORX)
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} \
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}
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AVX_RRM_TEST(VADDSS, "dword")
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AVX_RRM_TEST(VSUBSS, "dword")
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AVX_RRM_TEST(VMULSS, "dword")
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AVX_RRM_TEST(VDIVSS, "dword")
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AVX_RRM_TEST(VADDPS, "dqword")
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AVX_RRM_TEST(VSUBPS, "dqword")
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AVX_RRM_TEST(VMULPS, "dqword")
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AVX_RRM_TEST(VDIVPS, "dqword")
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AVX_RRM_TEST(VADDSD, "qword")
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AVX_RRM_TEST(VSUBSD, "qword")
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AVX_RRM_TEST(VMULSD, "qword")
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AVX_RRM_TEST(VDIVSD, "qword")
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AVX_RRM_TEST(VADDPD, "dqword")
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AVX_RRM_TEST(VSUBPD, "dqword")
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AVX_RRM_TEST(VMULPD, "dqword")
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AVX_RRM_TEST(VDIVPD, "dqword")
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AVX_RRM_TEST(VSQRTSD, "qword")
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AVX_RRM_TEST(VUNPCKLPS, "dqword")
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AVX_RRM_TEST(VUNPCKLPD, "dqword")
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AVX_RRM_TEST(VUNPCKHPD, "dqword")
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AVX_RRM_TEST(VANDPS, "dqword")
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AVX_RRM_TEST(VANDPD, "dqword")
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AVX_RRM_TEST(VANDNPS, "dqword")
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@ -1067,6 +1105,31 @@ FMA3_TEST(VFNMSUB, S, false)
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FMA3_TEST(VFMADDSUB, P, true)
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FMA3_TEST(VFMSUBADD, P, true)
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#define AVX_RRMI_TEST(Name, MemBits) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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for (const auto& r1 : xmmnames) \
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{ \
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for (const auto& r2 : xmmnames) \
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{ \
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for (const auto& r3 : xmmnames) \
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{ \
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emitter->Name(r1.reg, r2.reg, R(r3.reg), 0x0b); \
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ExpectDisassembly(#Name " " + r1.name + ", " + r2.name + ", " + r3.name + ", 0x0b"); \
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} \
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emitter->Name(r1.reg, r2.reg, MatR(R12), 0x0b); \
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ExpectDisassembly(#Name " " + r1.name + ", " + r2.name + \
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", " MemBits " ptr ds:[r12], 0x0b"); \
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} \
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} \
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}
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AVX_RRMI_TEST(VCMPPD, "dqword")
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AVX_RRMI_TEST(VSHUFPS, "dqword")
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AVX_RRMI_TEST(VSHUFPD, "dqword")
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AVX_RRMI_TEST(VBLENDPS, "dqword")
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AVX_RRMI_TEST(VBLENDPD, "dqword")
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// for VEX instructions that take the form op reg, reg, r/m, reg OR reg, reg, reg, r/m
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#define VEX_RRMR_RRRM_TEST(Name, sizename) \
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TEST_F(x64EmitterTest, Name) \
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