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Merge pull request #6592 from lioncash/imagine-le-ppc

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Interpreter_LoadStore: Generate alignment exceptions if lmw, lswi, lswx, stmw, stswi, or stswx is executed when the MSR[LE] bit is set
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Markus Wick 2018-04-04 09:00:45 +02:00 committed by GitHub
commit ba42238b0b
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 27 additions and 2 deletions
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29
Source/Core/Core/PowerPC/Interpreter/Interpreter_LoadStore.cpp
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@ -213,7 +213,7 @@ void Interpreter::lmw(UGeckoInstruction inst)
{
u32 address = Helper_Get_EA(inst);
if ((address & 0b11) != 0)
if ((address & 0b11) != 0 || UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(address);
return;
@ -241,7 +241,7 @@ void Interpreter::stmw(UGeckoInstruction inst)
{
u32 address = Helper_Get_EA(inst);
if ((address & 0b11) != 0)
if ((address & 0b11) != 0 || UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(address);
return;
@ -565,6 +565,12 @@ void Interpreter::lswx(UGeckoInstruction inst)
{
u32 EA = Helper_Get_EA_X(inst);
if (UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(EA);
return;
}
// Confirmed by hardware test that the zero case doesn't zero rGPR[r]
for (u32 n = 0; n < static_cast<u8>(PowerPC::ppcState.xer_stringctrl); n++)
{
@ -707,6 +713,12 @@ void Interpreter::lswi(UGeckoInstruction inst)
else
EA = rGPR[inst.RA];
if (UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(EA);
return;
}
u32 n;
if (inst.NB == 0)
n = 32;
@ -752,6 +764,12 @@ void Interpreter::stswi(UGeckoInstruction inst)
else
EA = rGPR[inst.RA];
if (UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(EA);
return;
}
u32 n;
if (inst.NB == 0)
n = 32;
@ -785,6 +803,13 @@ void Interpreter::stswi(UGeckoInstruction inst)
void Interpreter::stswx(UGeckoInstruction inst)
{
u32 EA = Helper_Get_EA_X(inst);
if (UReg_MSR{MSR}.LE)
{
GenerateAlignmentException(EA);
return;
}
u32 n = (u8)PowerPC::ppcState.xer_stringctrl;
int r = inst.RS;
int i = 0;