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JIT64: faster + branchless crxxx
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Fiora
parent
8c71703098
commit
c936984c96
@ -104,8 +104,8 @@ public:
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// Reads a given bit of a given CR register part. Clobbers ABI_PARAM1,
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// don't forget to xlock it before.
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void GetCRFieldBit(int field, int bit, Gen::X64Reg out);
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// Clobbers ABI_PARAM1 and ABI_PARAM2, xlock them before.
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void GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate = false);
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// Clobbers ABI_PARAM1, xlock it before.
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void SetCRFieldBit(int field, int bit, Gen::X64Reg in);
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// Generates a branch that will check if a given bit of a CR register part
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@ -11,31 +11,28 @@
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using namespace Gen;
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void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out)
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void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate)
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{
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switch (bit)
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{
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(CC_NZ, R(out));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(61));
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SETcc(negate ? CC_NC : CC_C, R(out));
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break;
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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SETcc(CC_Z, R(out));
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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SETcc(negate ? CC_NZ : CC_Z, R(out));
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break;
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case CR_GT_BIT: // check val > 0
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MOV(64, R(ABI_PARAM1), M(&PowerPC::ppcState.cr_val[field]));
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TEST(64, R(ABI_PARAM1), R(ABI_PARAM1));
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SETcc(CC_G, R(out));
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CMP(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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SETcc(negate ? CC_NG : CC_G, R(out));
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break;
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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SETcc(CC_NZ, R(out));
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(62));
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SETcc(negate ? CC_NC : CC_C, R(out));
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break;
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default:
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@ -45,63 +42,40 @@ void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out)
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void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in)
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{
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MOV(64, R(ABI_PARAM2), M(&PowerPC::ppcState.cr_val[field]));
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TEST(8, R(in), Imm8(1));
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FixupBranch input_is_set = J_CC(CC_NZ, false);
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// New value is 0.
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switch (bit)
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{
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case CR_SO_BIT: // unset bit 61
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 61)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case CR_EQ_BIT: // set bit 0 to 1
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OR(8, R(ABI_PARAM2), Imm8(1));
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break;
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case CR_GT_BIT: // !GT, set bit 63
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 63));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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case CR_LT_BIT: // !LT, unset bit 62
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 62)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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break;
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}
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FixupBranch end = J();
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SetJumpTarget(input_is_set);
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MOV(64, R(ABI_PARAM1), M(&PowerPC::ppcState.cr_val[field]));
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MOVZX(32, 8, in, R(in));
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switch (bit)
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{
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case CR_SO_BIT: // set bit 61
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 61));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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case CR_SO_BIT: // set bit 61 to input
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BTR(64, R(ABI_PARAM1), Imm8(61));
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SHL(64, R(in), Imm8(61));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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case CR_EQ_BIT: // set bits 31-0 to 0
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MOV(64, R(ABI_PARAM1), Imm64(0xFFFFFFFF00000000));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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case CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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SHR(64, R(ABI_PARAM1), Imm8(32));
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SHL(64, R(ABI_PARAM1), Imm8(32));
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XOR(32, R(in), Imm8(1));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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case CR_GT_BIT: // unset bit 63
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MOV(64, R(ABI_PARAM1), Imm64(~(1ull << 63)));
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AND(64, R(ABI_PARAM2), R(ABI_PARAM1));
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case CR_GT_BIT: // set bit 63 to !input
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BTR(64, R(ABI_PARAM1), Imm8(63));
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NOT(32, R(in));
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SHL(64, R(in), Imm8(63));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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case CR_LT_BIT: // set bit 62
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 62));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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case CR_LT_BIT: // set bit 62 to input
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BTR(64, R(ABI_PARAM1), Imm8(62));
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SHL(64, R(in), Imm8(62));
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OR(64, R(ABI_PARAM1), R(in));
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break;
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}
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SetJumpTarget(end);
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MOV(64, R(ABI_PARAM1), Imm64(1ull << 32));
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OR(64, R(ABI_PARAM2), R(ABI_PARAM1));
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MOV(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM2));
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BTS(64, R(ABI_PARAM1), Imm8(32));
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MOV(64, M(&PowerPC::ppcState.cr_val[field]), R(ABI_PARAM1));
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}
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FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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@ -109,23 +83,20 @@ FixupBranch Jit64::JumpIfCRFieldBit(int field, int bit, bool jump_if_set)
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switch (bit)
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{
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case CR_SO_BIT: // check bit 61 set
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MOV(64, R(RAX), Imm64(1ull << 61));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(61));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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case CR_EQ_BIT: // check bits 31-0 == 0
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm32(0));
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CMP(32, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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return J_CC(jump_if_set ? CC_Z : CC_NZ, true);
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case CR_GT_BIT: // check val > 0
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MOV(64, R(RAX), M(&PowerPC::ppcState.cr_val[field]));
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TEST(64, R(RAX), R(RAX));
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CMP(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(0));
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return J_CC(jump_if_set ? CC_G : CC_LE, true);
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case CR_LT_BIT: // check bit 62 set
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MOV(64, R(RAX), Imm64(1ull << 62));
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TEST(64, M(&PowerPC::ppcState.cr_val[field]), R(RAX));
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return J_CC(jump_if_set ? CC_NZ : CC_Z, true);
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BT(64, M(&PowerPC::ppcState.cr_val[field]), Imm8(62));
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return J_CC(jump_if_set ? CC_C : CC_NC, true);
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default:
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_assert_msg_(DYNA_REC, false, "Invalid CR bit");
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@ -458,49 +429,33 @@ void Jit64::crXXX(UGeckoInstruction inst)
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// not required.
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// USES_CR
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// crandc or crorc or creqv or crnand or crnor
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bool negateA = inst.SUBOP10 == 129 || inst.SUBOP10 == 417 || inst.SUBOP10 == 289 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// crnand or crnor
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bool negateB = inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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gpr.FlushLockX(ABI_PARAM1, ABI_PARAM2);
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GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), ABI_PARAM2);
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GetCRFieldBit(inst.CRBB >> 2, 3 - (inst.CRBB & 3), EAX);
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gpr.FlushLockX(ABI_PARAM1);
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GetCRFieldBit(inst.CRBA >> 2, 3 - (inst.CRBA & 3), ABI_PARAM1, negateA);
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GetCRFieldBit(inst.CRBB >> 2, 3 - (inst.CRBB & 3), EAX, negateB);
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// Compute combined bit
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switch (inst.SUBOP10)
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{
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case 33: // crnor
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OR(8, R(EAX), R(ABI_PARAM2));
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NOT(8, R(EAX));
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break;
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case 33: // crnor: ~(A || B) == (~A && ~B)
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case 129: // crandc
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NOT(8, R(ABI_PARAM2));
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AND(8, R(EAX), R(ABI_PARAM2));
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case 257: // crand
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AND(8, R(EAX), R(ABI_PARAM1));
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break;
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case 193: // crxor
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XOR(8, R(EAX), R(ABI_PARAM2));
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break;
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case 225: // crnand
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AND(8, R(EAX), R(ABI_PARAM2));
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NOT(8, R(EAX));
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break;
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case 257: // crand
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AND(8, R(EAX), R(ABI_PARAM2));
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break;
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case 289: // creqv
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XOR(8, R(EAX), R(ABI_PARAM2));
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NOT(8, R(EAX));
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XOR(8, R(EAX), R(ABI_PARAM1));
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break;
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case 225: // crnand: ~(A && B) == (~A || ~B)
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case 417: // crorc
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NOT(8, R(ABI_PARAM2));
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OR(8, R(EAX), R(ABI_PARAM2));
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break;
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case 449: // cror
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OR(8, R(EAX), R(ABI_PARAM2));
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OR(8, R(EAX), R(ABI_PARAM1));
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break;
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}
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