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https://github.com/dolphin-emu/dolphin.git
synced 2024-11-14 21:37:52 -07:00
Should fix crashes caused by aram dma reading off the end of our aram size.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4958 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
Shawn Hoffman
parent
e3730a2440
commit
cdb829edd5
@ -60,9 +60,9 @@ enum
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DSP_MAIL_FROM_DSP_LO = 0x5006,
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DSP_CONTROL = 0x500A,
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DSP_INTERRUPT_CONTROL = 0x5010,
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AR_SIZE = 0x5012, // These names are a good guess at best
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AR_INFO = 0x5012, // These names are a good guess at best
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AR_MODE = 0x5016, //
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AR_REFRESH = 0x501a, //
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AR_REFRESH = 0x501a,
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AR_DMA_MMADDR_H = 0x5020,
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AR_DMA_MMADDR_L = 0x5022,
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AR_DMA_ARADDR_H = 0x5024,
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@ -83,7 +83,7 @@ union UARAMCount
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struct
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{
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u32 count : 31;
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u32 dir : 1; // 0: MRAM -> ARAM 1: ARAM -> MRAM
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u32 dir : 1; // 0: MRAM -> ARAM 1: ARAM -> MRAM
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};
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};
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@ -92,22 +92,25 @@ union UARAMCount
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union UDSPControl
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{
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u16 Hex;
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struct
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struct
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{
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// DSP Control
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u16 DSPReset : 1; // Write 1 to reset and waits for 0
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u16 DSPAssertInt : 1;
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u16 DSPHalt : 1;
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// Interrupt for DMA to the AI/speakers
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u16 AID : 1;
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u16 AID_mask : 1;
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// ARAM DMA interrupt
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u16 ARAM : 1;
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u16 ARAM_mask : 1;
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// DSP DMA interrupt
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u16 DSP : 1;
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u16 DSP_mask : 1;
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u16 ARAM_DMAState : 1; // DSPGetDMAStatus() uses this flag
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// Other ???
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u16 DMAState : 1; // DSPGetDMAStatus() uses this flag. __ARWaitForDMA() uses it too...maybe it's just general DMA flag
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u16 unk3 : 1;
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u16 DSPInit : 1; // DSPInit() writes to this flag (1 as long as dsp PC is in IROM?)
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u16 DSPInit : 1; // DSPInit() writes to this flag
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u16 pad : 4;
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};
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};
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@ -190,7 +193,21 @@ static ARAMInfo g_ARAM;
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static DSPState g_dspState;
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static AudioDMA g_audioDMA;
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static ARAM_DMA g_arDMA;
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static u16 g_AR_SIZE;
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union ARAM_Info
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{
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u16 Hex;
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struct
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{
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u16 size : 6;
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u16 unk : 1;
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u16 : 9;
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};
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};
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static ARAM_Info g_ARAM_Info;
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// Contains bitfields for some stuff we don't care about (and nothing ever reads):
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// CAS latency/burst length/addressing mode/write mode
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// We care about the LSB tho. It indicates that the ARAM controller has finished initializing
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static u16 g_AR_MODE;
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static u16 g_AR_REFRESH;
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@ -204,7 +221,7 @@ void DoState(PointerWrap &p)
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p.Do(g_dspState);
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p.Do(g_audioDMA);
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p.Do(g_arDMA);
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p.Do(g_AR_SIZE);
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p.Do(g_ARAM_Info);
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p.Do(g_AR_MODE);
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p.Do(g_AR_REFRESH);
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}
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@ -249,9 +266,9 @@ void Init()
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g_dspState.DSPControl.Hex = 0;
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g_dspState.DSPControl.DSPHalt = 1;
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g_AR_SIZE = 0;
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g_AR_MODE = 1; // Means that aram controller has finished initializing the mem
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g_AR_REFRESH = 0;
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g_ARAM_Info.Hex = 0;
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g_AR_MODE = 1; // ARAM Controller has init'd
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g_AR_REFRESH = 156; // 156MHz
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et_GenerateDSPInterrupt = CoreTiming::RegisterEvent("DSPint", GenerateDSPInterrupt_Wrapper);
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}
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@ -269,7 +286,7 @@ void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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switch (_iAddress & 0xFFFF)
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{
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// AI_REGS 0x5000+
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// DSP
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case DSP_MAIL_TO_DSP_HI:
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_uReturnValue = dsp_plugin->DSP_ReadMailboxHigh(true);
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break;
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@ -291,9 +308,10 @@ void Read16(u16& _uReturnValue, const u32 _iAddress)
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(dsp_plugin->DSP_ReadControlRegister() & DSP_CONTROL_MASK);
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break;
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// AR_REGS 0x501x+
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case AR_SIZE:
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_uReturnValue = g_AR_SIZE;
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// ARAM
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case AR_INFO:
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PanicAlert("read %x %x", g_ARAM_Info.Hex,PowerPC::ppcState.pc);
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_uReturnValue = g_ARAM_Info.Hex;
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break;
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case AR_MODE:
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@ -311,7 +329,7 @@ void Read16(u16& _uReturnValue, const u32 _iAddress)
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case AR_DMA_CNT_H: _uReturnValue = g_arDMA.Cnt.Hex >> 16; return;
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case AR_DMA_CNT_L: _uReturnValue = g_arDMA.Cnt.Hex & 0xFFFF; return;
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// DMA_REGS 0x5030+
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// AI
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case AUDIO_DMA_BLOCKS_LEFT:
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_uReturnValue = g_audioDMA.BlocksLeft;
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break;
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@ -345,7 +363,7 @@ void Write16(const u16 _Value, const u32 _Address)
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switch (_Address & 0xFFFF)
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{
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// DSP Regs 0x5000+
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// DSP
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case DSP_MAIL_TO_DSP_HI:
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dsp_plugin->DSP_WriteMailboxHigh(true, _Value);
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break;
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@ -386,7 +404,7 @@ void Write16(const u16 _Value, const u32 _Address)
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if (tmpControl.DSP) g_dspState.DSPControl.DSP = 0;
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// g_ARAM
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g_dspState.DSPControl.ARAM_DMAState = 0; // keep g_ARAM DMA State zero
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g_dspState.DSPControl.DMAState = 0; // keep g_ARAM DMA State zero
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// unknown
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g_dspState.DSPControl.unk3 = tmpControl.unk3;
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@ -400,16 +418,15 @@ void Write16(const u16 _Value, const u32 _Address)
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}
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break;
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// AR_REGS 0x501x+
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// ARAM
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// DMA back and forth between ARAM and RAM
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case AR_SIZE:
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g_AR_SIZE = _Value;
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// __OSInitAudioSystem sets to 0x43
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case AR_INFO:
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PanicAlert("write %x %x", _Value,PowerPC::ppcState.pc);
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g_ARAM_Info.Hex = _Value;
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// __OSInitAudioSystem sets to 0x43 -> expects 16bit adressing and mapping to dsp iram?
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// __OSCheckSize sets = 0x20 | 3 (keeps upper bits)
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// 0x23 -> Zelda standard mode (standard ARAM access ??)
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// 0x63 -> ARCheckSize Mode (access AR-registers ??) or no exception ??
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// probably bitfield for: CAS latency/burst length/addressing mode/write mode
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// In any case, the aram driver should set it up :}
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break;
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case AR_MODE:
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@ -436,16 +453,10 @@ void Write16(const u16 _Value, const u32 _Address)
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case AR_DMA_CNT_L:
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g_arDMA.Cnt.Hex = (g_arDMA.Cnt.Hex & 0xFFFF0000) | (_Value);
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if (g_arDMA.Cnt.count % 8)
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{
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PanicAlert("DSPINTERFACE: ARAM DMA count: %08x not aligned to 8 bytes!", g_arDMA.Cnt.Hex);
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ERROR_LOG(DSPINTERFACE, "ARAM DMA count: %08x not aligned to 8 bytes!", g_arDMA.Cnt.Hex);
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}
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else
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Do_ARAM_DMA();
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Do_ARAM_DMA();
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break;
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// Audio DMA_REGS 0x5030+
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// AI
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// This is the DMA that goes straight out the speaker.
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case AUDIO_DMA_START_HI:
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g_audioDMA.SourceAddress = (g_audioDMA.SourceAddress & 0xFFFF) | (_Value<<16);
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@ -477,6 +488,7 @@ void Read32(u32& _uReturnValue, const u32 _iAddress)
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INFO_LOG(DSPINTERFACE, "DSPInterface(r32) 0x%08x", _iAddress);
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switch (_iAddress & 0xFFFF)
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{
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// DSP
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case DSP_MAIL_TO_DSP_HI:
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_uReturnValue = (dsp_plugin->DSP_ReadMailboxHigh(true) << 16) | dsp_plugin->DSP_ReadMailboxLow(true);
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break;
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@ -494,17 +506,18 @@ void Write32(const u32 _iValue, const u32 _iAddress)
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switch (_iAddress & 0xFFFF)
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{
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// DSP
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case DSP_MAIL_TO_DSP_HI:
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dsp_plugin->DSP_WriteMailboxHigh(true, _iValue >> 16);
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dsp_plugin->DSP_WriteMailboxLow(true, (u16)_iValue);
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break;
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// AI
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case AUDIO_DMA_START_HI:
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g_audioDMA.SourceAddress = _iValue;
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break;
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// AR_REGS - i dont know why they are accessed 32 bit too ...
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// Answer: simply because they can be
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// ARAM
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case AR_DMA_MMADDR_H:
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g_arDMA.MMAddr = _iValue;
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break;
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@ -515,13 +528,7 @@ void Write32(const u32 _iValue, const u32 _iAddress)
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case AR_DMA_CNT_H:
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g_arDMA.Cnt.Hex = _iValue;
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if (g_arDMA.Cnt.count % 8)
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{
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PanicAlert("DSPINTERFACE: ARAM DMA count: %08x not aligned to 8 bytes!", g_arDMA.Cnt.Hex);
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ERROR_LOG(DSPINTERFACE, "ARAM DMA count: %08x not aligned to 8 bytes!", g_arDMA.Cnt.Hex);
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}
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else
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Do_ARAM_DMA();
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Do_ARAM_DMA();
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break;
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default:
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@ -579,15 +586,15 @@ void UpdateAudioDMA()
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if (g_audioDMA.BlocksLeft == g_audioDMA.AudioDMAControl.NumBlocks)
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dsp_plugin->DSP_SendAIBuffer(g_audioDMA.SourceAddress, g_audioDMA.AudioDMAControl.NumBlocks * 8);
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// g_audioDMA.ReadAddress += 32;
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//g_audioDMA.ReadAddress += 32;
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g_audioDMA.BlocksLeft--;
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if (g_audioDMA.BlocksLeft == 0)
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{
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GenerateDSPInterrupt(DSP::INT_AID);
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// g_audioDMA.ReadAddress = g_audioDMA.SourceAddress;
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//g_audioDMA.ReadAddress = g_audioDMA.SourceAddress;
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g_audioDMA.BlocksLeft = g_audioDMA.AudioDMAControl.NumBlocks;
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// DEBUG_LOG(DSPLLE, "ADMA read addresses: %08x", g_audioDMA.ReadAddress);
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//DEBUG_LOG(DSPLLE, "ADMA read addresses: %08x", g_audioDMA.ReadAddress);
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}
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}
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else
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@ -609,9 +616,12 @@ void Do_ARAM_DMA()
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while (g_arDMA.Cnt.count)
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{
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Memory::Write_U64_Swap(*(u64*)&g_ARAM.ptr[g_arDMA.ARAddr], g_arDMA.MMAddr);
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g_arDMA.MMAddr += 8;
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g_arDMA.ARAddr += 8;
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if (g_arDMA.ARAddr < g_ARAM.size)
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{
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Memory::Write_U64_Swap(*(u64*)&g_ARAM.ptr[g_arDMA.ARAddr], g_arDMA.MMAddr);
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g_arDMA.MMAddr += 8;
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g_arDMA.ARAddr += 8;
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}
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g_arDMA.Cnt.count -= 8;
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}
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}
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