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JitArm64_SystemRegisters: Use ScopedARM64Reg
This commit is contained in:
Sintendo
parent
be2b466743
commit
defb2d65a6
@ -48,17 +48,16 @@ void JitArm64::FixGTBeforeSettingCRFieldBit(Arm64Gen::ARM64Reg reg)
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// if the internal representation either has bit 63 set or has all bits set to zero.
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// If all bits are zero and we set some bit that's unrelated to GT, we need to set bit 63 so GT
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// doesn't accidentally become considered set. Gross but necessary; this can break actual games.
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ORR(XA, reg, LogicalImm(1ULL << 63, GPRSize::B64));
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CMP(reg, ARM64Reg::ZR);
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CSEL(reg, reg, XA, CC_NEQ);
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gpr.Unlock(WA);
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}
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void JitArm64::UpdateFPExceptionSummary(ARM64Reg fpscr)
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{
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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// fpscr.VX = (fpscr & FPSCR_VX_ANY) != 0
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MOVI2R(WA, FPSCR_VX_ANY);
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@ -71,8 +70,6 @@ void JitArm64::UpdateFPExceptionSummary(ARM64Reg fpscr)
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TST(WA, fpscr, ArithOption(fpscr, ShiftType::LSR, 22));
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CSET(WA, CCFlags::CC_NEQ);
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BFI(fpscr, WA, MathUtil::IntLog2(FPSCR_FEX), 1);
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gpr.Unlock(WA);
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}
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void JitArm64::UpdateRoundingMode()
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@ -135,7 +132,7 @@ void JitArm64::mcrxr(UGeckoInstruction inst)
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JITDISABLE(bJITSystemRegistersOff);
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gpr.BindCRToRegister(inst.CRFD, false);
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg XB = gpr.CR(inst.CRFD);
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ARM64Reg WB = EncodeRegTo32(XB);
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@ -155,8 +152,6 @@ void JitArm64::mcrxr(UGeckoInstruction inst)
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// Clear XER[0-3]
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static_assert(PPCSTATE_OFF(xer_ca) + 1 == PPCSTATE_OFF(xer_so_ov));
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STRH(IndexType::Unsigned, ARM64Reg::WZR, PPC_REG, PPCSTATE_OFF(xer_ca));
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gpr.Unlock(WA);
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}
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void JitArm64::mfsr(UGeckoInstruction inst)
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@ -186,14 +181,12 @@ void JitArm64::mfsrin(UGeckoInstruction inst)
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ARM64Reg RB = gpr.R(b);
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ARM64Reg RD = gpr.R(d);
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ARM64Reg index = gpr.GetReg();
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auto index = gpr.GetScopedReg();
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ARM64Reg addr = EncodeRegTo64(RD);
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UBFM(index, RB, 28, 31);
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ADDI2R(addr, PPC_REG, PPCSTATE_OFF_SR(0), addr);
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LDR(RD, addr, ArithOption(EncodeRegTo64(index), true));
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gpr.Unlock(index);
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}
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void JitArm64::mtsrin(UGeckoInstruction inst)
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@ -206,14 +199,12 @@ void JitArm64::mtsrin(UGeckoInstruction inst)
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ARM64Reg RB = gpr.R(b);
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ARM64Reg RD = gpr.R(d);
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ARM64Reg index = gpr.GetReg();
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ARM64Reg addr = gpr.GetReg();
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auto index = gpr.GetScopedReg();
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auto addr = gpr.GetScopedReg();
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UBFM(index, RB, 28, 31);
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ADDI2R(EncodeRegTo64(addr), PPC_REG, PPCSTATE_OFF_SR(0), EncodeRegTo64(addr));
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STR(RD, EncodeRegTo64(addr), ArithOption(EncodeRegTo64(index), true));
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gpr.Unlock(index, addr);
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}
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void JitArm64::twx(UGeckoInstruction inst)
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@ -223,7 +214,7 @@ void JitArm64::twx(UGeckoInstruction inst)
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s32 a = inst.RA;
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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if (inst.OPCD == 3) // twi
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{
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@ -278,8 +269,6 @@ void JitArm64::twx(UGeckoInstruction inst)
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fpr.Flush(FlushMode::All, ARM64Reg::INVALID_REG);
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WriteExit(js.compilerPC + 4);
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}
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gpr.Unlock(WA);
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}
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void JitArm64::mfspr(UGeckoInstruction inst)
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@ -294,19 +283,19 @@ void JitArm64::mfspr(UGeckoInstruction inst)
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case SPR_TL:
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case SPR_TU:
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{
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ARM64Reg Wg = gpr.GetReg();
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auto Wg = gpr.GetScopedReg();
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ARM64Reg Xg = EncodeRegTo64(Wg);
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ARM64Reg Wresult = gpr.GetReg();
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auto Wresult = gpr.GetScopedReg();
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ARM64Reg Xresult = EncodeRegTo64(Wresult);
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ARM64Reg WA = gpr.GetReg();
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ARM64Reg WB = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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auto WB = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg XB = EncodeRegTo64(WB);
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ARM64Reg VC = fpr.GetReg();
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ARM64Reg VD = fpr.GetReg();
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auto VC = fpr.GetScopedReg();
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auto VD = fpr.GetScopedReg();
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ARM64Reg SC = EncodeRegToSingle(VC);
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ARM64Reg SD = EncodeRegToSingle(VD);
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@ -371,8 +360,6 @@ void JitArm64::mfspr(UGeckoInstruction inst)
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else
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LSR(EncodeRegTo64(gpr.R(n)), Xresult, 32);
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gpr.Unlock(Wg, Wresult, WA, WB);
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fpr.Unlock(VC, VD);
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break;
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}
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}
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@ -381,22 +368,18 @@ void JitArm64::mfspr(UGeckoInstruction inst)
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LSR(EncodeRegTo64(gpr.R(d)), Xresult, 32);
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else
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MOV(gpr.R(d), Wresult);
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gpr.Unlock(Wg, Wresult, WA, WB);
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fpr.Unlock(VC, VD);
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}
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break;
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case SPR_XER:
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{
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gpr.BindToRegister(d, false);
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ARM64Reg RD = gpr.R(d);
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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LDRH(IndexType::Unsigned, RD, PPC_REG, PPCSTATE_OFF(xer_stringctrl));
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LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_ca));
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ORR(RD, RD, WA, ArithOption(WA, ShiftType::LSL, XER_CA_SHIFT));
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LDRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_so_ov));
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ORR(RD, RD, WA, ArithOption(WA, ShiftType::LSL, XER_OV_SHIFT));
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gpr.Unlock(WA);
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}
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break;
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case SPR_WPAR:
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@ -462,14 +445,13 @@ void JitArm64::mtspr(UGeckoInstruction inst)
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case SPR_XER:
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{
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ARM64Reg RD = gpr.R(inst.RD);
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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AND(WA, RD, LogicalImm(0xFFFFFF7F, GPRSize::B32));
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STRH(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_stringctrl));
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UBFM(WA, RD, XER_CA_SHIFT, XER_CA_SHIFT + 1);
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STRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_ca));
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UBFM(WA, RD, XER_OV_SHIFT, 31); // Same as WA = RD >> XER_OV_SHIFT
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STRB(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(xer_so_ov));
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gpr.Unlock(WA);
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}
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break;
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default:
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@ -553,114 +535,112 @@ void JitArm64::crXXX(UGeckoInstruction inst)
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return;
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}
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg WB = gpr.GetReg();
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ARM64Reg XB = EncodeRegTo64(WB);
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// creqv or crnand or crnor
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bool negateA = inst.SUBOP10 == 289 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// crandc or crorc or crnand or crnor
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bool negateB =
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inst.SUBOP10 == 129 || inst.SUBOP10 == 417 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// GetCRFieldBit
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for (int i = 0; i < 2; i++)
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{
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int field = i ? inst.CRBB >> 2 : inst.CRBA >> 2;
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int bit = i ? 3 - (inst.CRBB & 3) : 3 - (inst.CRBA & 3);
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ARM64Reg out = i ? XB : XA;
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bool negate = i ? negateB : negateA;
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auto WB = gpr.GetScopedReg();
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ARM64Reg XB = EncodeRegTo64(WB);
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ARM64Reg XC = gpr.CR(field);
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ARM64Reg WC = EncodeRegTo32(XC);
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switch (bit)
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// creqv or crnand or crnor
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bool negateA = inst.SUBOP10 == 289 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// crandc or crorc or crnand or crnor
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bool negateB =
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inst.SUBOP10 == 129 || inst.SUBOP10 == 417 || inst.SUBOP10 == 225 || inst.SUBOP10 == 33;
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// GetCRFieldBit
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for (int i = 0; i < 2; i++)
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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UBFX(out, XC, PowerPC::CR_EMU_SO_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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int field = i ? inst.CRBB >> 2 : inst.CRBA >> 2;
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int bit = i ? 3 - (inst.CRBB & 3) : 3 - (inst.CRBA & 3);
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ARM64Reg out = i ? XB : XA;
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bool negate = i ? negateB : negateA;
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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CMP(WC, ARM64Reg::WZR);
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CSET(out, negate ? CC_NEQ : CC_EQ);
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break;
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ARM64Reg XC = gpr.CR(field);
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ARM64Reg WC = EncodeRegTo32(XC);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // check bit 59 set
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UBFX(out, XC, PowerPC::CR_EMU_SO_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT: // check val > 0
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CMP(XC, ARM64Reg::ZR);
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CSET(out, negate ? CC_LE : CC_GT);
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break;
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case PowerPC::CR_EQ_BIT: // check bits 31-0 == 0
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CMP(WC, ARM64Reg::WZR);
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CSET(out, negate ? CC_NEQ : CC_EQ);
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break;
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case PowerPC::CR_LT_BIT: // check bit 62 set
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UBFX(out, XC, PowerPC::CR_EMU_LT_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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case PowerPC::CR_GT_BIT: // check val > 0
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CMP(XC, ARM64Reg::ZR);
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CSET(out, negate ? CC_LE : CC_GT);
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break;
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default:
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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case PowerPC::CR_LT_BIT: // check bit 62 set
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UBFX(out, XC, PowerPC::CR_EMU_LT_BIT, 1);
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if (negate)
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EOR(out, out, LogicalImm(1, GPRSize::B64));
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break;
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default:
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ASSERT_MSG(DYNA_REC, false, "Invalid CR bit");
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}
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}
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}
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// Compute combined bit
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switch (inst.SUBOP10)
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{
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case 33: // crnor: ~(A || B) == (~A && ~B)
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case 129: // crandc: A && ~B
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case 257: // crand: A && B
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AND(XA, XA, XB);
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break;
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// Compute combined bit
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switch (inst.SUBOP10)
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{
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case 33: // crnor: ~(A || B) == (~A && ~B)
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case 129: // crandc: A && ~B
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case 257: // crand: A && B
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AND(XA, XA, XB);
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break;
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case 193: // crxor: A ^ B
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case 289: // creqv: ~(A ^ B) = ~A ^ B
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EOR(XA, XA, XB);
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break;
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case 193: // crxor: A ^ B
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case 289: // creqv: ~(A ^ B) = ~A ^ B
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EOR(XA, XA, XB);
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break;
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case 225: // crnand: ~(A && B) == (~A || ~B)
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case 417: // crorc: A || ~B
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case 449: // cror: A || B
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ORR(XA, XA, XB);
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break;
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case 225: // crnand: ~(A && B) == (~A || ~B)
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case 417: // crorc: A || ~B
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case 449: // cror: A || B
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ORR(XA, XA, XB);
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break;
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}
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}
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// Store result bit in CRBD
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int field = inst.CRBD >> 2;
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int bit = 3 - (inst.CRBD & 3);
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gpr.Unlock(WB);
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WB = ARM64Reg::INVALID_REG;
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gpr.BindCRToRegister(field, true);
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XB = gpr.CR(field);
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ARM64Reg CR = gpr.CR(field);
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if (bit != PowerPC::CR_GT_BIT)
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FixGTBeforeSettingCRFieldBit(XB);
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FixGTBeforeSettingCRFieldBit(CR);
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switch (bit)
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{
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case PowerPC::CR_SO_BIT: // set bit 59 to input
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BFI(XB, XA, PowerPC::CR_EMU_SO_BIT, 1);
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BFI(CR, XA, PowerPC::CR_EMU_SO_BIT, 1);
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break;
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case PowerPC::CR_EQ_BIT: // clear low 32 bits, set bit 0 to !input
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AND(XB, XB, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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AND(CR, CR, LogicalImm(0xFFFF'FFFF'0000'0000, GPRSize::B64));
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EOR(XA, XA, LogicalImm(1, GPRSize::B64));
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ORR(XB, XB, XA);
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ORR(CR, CR, XA);
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break;
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case PowerPC::CR_GT_BIT: // set bit 63 to !input
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EOR(XA, XA, LogicalImm(1, GPRSize::B64));
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BFI(XB, XA, 63, 1);
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BFI(CR, XA, 63, 1);
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break;
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case PowerPC::CR_LT_BIT: // set bit 62 to input
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BFI(XB, XA, PowerPC::CR_EMU_LT_BIT, 1);
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BFI(CR, XA, PowerPC::CR_EMU_LT_BIT, 1);
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break;
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}
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ORR(XB, XB, LogicalImm(1ULL << 32, GPRSize::B64));
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gpr.Unlock(WA);
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ORR(CR, CR, LogicalImm(1ULL << 32, GPRSize::B64));
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}
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void JitArm64::mfcr(UGeckoInstruction inst)
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@ -670,8 +650,8 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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gpr.BindToRegister(inst.RD, false);
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ARM64Reg WA = gpr.R(inst.RD);
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ARM64Reg WB = gpr.GetReg();
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ARM64Reg WC = gpr.GetReg();
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auto WB = gpr.GetScopedReg();
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auto WC = gpr.GetScopedReg();
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ARM64Reg XA = EncodeRegTo64(WA);
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ARM64Reg XB = EncodeRegTo64(WB);
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ARM64Reg XC = EncodeRegTo64(WC);
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@ -716,8 +696,6 @@ void JitArm64::mfcr(UGeckoInstruction inst)
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else if (!js.op->crInUse[i])
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gpr.StoreCRRegisters(BitSet8{i}, WC);
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}
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gpr.Unlock(WB, WC);
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}
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void JitArm64::mtcrf(UGeckoInstruction inst)
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@ -729,7 +707,7 @@ void JitArm64::mtcrf(UGeckoInstruction inst)
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if (crm != 0)
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{
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ARM64Reg RS = gpr.R(inst.RS);
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ARM64Reg WB = gpr.GetReg();
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auto WB = gpr.GetScopedReg();
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ARM64Reg XB = EncodeRegTo64(WB);
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MOVP2R(XB, PowerPC::ConditionRegister::s_crTable.data());
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for (int i = 0; i < 8; ++i)
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@ -753,7 +731,6 @@ void JitArm64::mtcrf(UGeckoInstruction inst)
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LDR(CR, XB, ArithOption(CR, true));
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}
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}
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gpr.Unlock(WB);
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}
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}
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@ -771,7 +748,7 @@ void JitArm64::mcrfs(UGeckoInstruction inst)
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gpr.BindCRToRegister(field, false);
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ARM64Reg CR = gpr.CR(field);
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ARM64Reg WA = gpr.GetReg();
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auto WA = gpr.GetScopedReg();
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ARM64Reg WCR = EncodeRegTo32(CR);
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ARM64Reg XA = EncodeRegTo64(WA);
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@ -789,8 +766,6 @@ void JitArm64::mcrfs(UGeckoInstruction inst)
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MOVP2R(XA, PowerPC::ConditionRegister::s_crTable.data());
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LDR(CR, XA, ArithOption(CR, true));
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gpr.Unlock(WA);
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}
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void JitArm64::mffsx(UGeckoInstruction inst)
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@ -799,7 +774,7 @@ void JitArm64::mffsx(UGeckoInstruction inst)
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JITDISABLE(bJITSystemRegistersOff);
|
||||
FALLBACK_IF(inst.Rc);
|
||||
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
auto WA = gpr.GetScopedReg();
|
||||
ARM64Reg XA = EncodeRegTo64(WA);
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
@ -808,8 +783,6 @@ void JitArm64::mffsx(UGeckoInstruction inst)
|
||||
|
||||
ORR(XA, XA, LogicalImm(0xFFF8'0000'0000'0000, GPRSize::B64));
|
||||
m_float_emit.FMOV(EncodeRegToDouble(VD), XA);
|
||||
|
||||
gpr.Unlock(WA);
|
||||
}
|
||||
|
||||
void JitArm64::mtfsb0x(UGeckoInstruction inst)
|
||||
@ -824,17 +797,17 @@ void JitArm64::mtfsb0x(UGeckoInstruction inst)
|
||||
if (mask == FPSCR_FEX || mask == FPSCR_VX)
|
||||
return;
|
||||
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
{
|
||||
auto WA = gpr.GetScopedReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
|
||||
if ((mask & (FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
gpr.Unlock(WA);
|
||||
if ((mask & (FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
}
|
||||
|
||||
if (inst.CRBD >= 29)
|
||||
UpdateRoundingMode();
|
||||
@ -852,25 +825,24 @@ void JitArm64::mtfsb1x(UGeckoInstruction inst)
|
||||
if (mask == FPSCR_FEX || mask == FPSCR_VX)
|
||||
return;
|
||||
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
if ((mask & FPSCR_ANY_X) != 0)
|
||||
{
|
||||
ARM64Reg WB = gpr.GetReg();
|
||||
TST(WA, LogicalImm(mask, GPRSize::B32));
|
||||
ORR(WB, WA, LogicalImm(1 << 31, GPRSize::B32));
|
||||
CSEL(WA, WA, WB, CCFlags::CC_NEQ);
|
||||
gpr.Unlock(WB);
|
||||
auto WA = gpr.GetScopedReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
if ((mask & FPSCR_ANY_X) != 0)
|
||||
{
|
||||
auto WB = gpr.GetScopedReg();
|
||||
TST(WA, LogicalImm(mask, GPRSize::B32));
|
||||
ORR(WB, WA, LogicalImm(1 << 31, GPRSize::B32));
|
||||
CSEL(WA, WA, WB, CCFlags::CC_NEQ);
|
||||
}
|
||||
ORR(WA, WA, LogicalImm(mask, GPRSize::B32));
|
||||
|
||||
if ((mask & (FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
}
|
||||
ORR(WA, WA, LogicalImm(mask, GPRSize::B32));
|
||||
|
||||
if ((mask & (FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
gpr.Unlock(WA);
|
||||
|
||||
if (inst.CRBD >= 29)
|
||||
UpdateRoundingMode();
|
||||
@ -887,32 +859,31 @@ void JitArm64::mtfsfix(UGeckoInstruction inst)
|
||||
u8 shift = 28 - 4 * inst.CRFD;
|
||||
u32 mask = 0xF << shift;
|
||||
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
if (imm == 0xF)
|
||||
{
|
||||
ORR(WA, WA, LogicalImm(mask, GPRSize::B32));
|
||||
}
|
||||
else if (imm == 0x0)
|
||||
{
|
||||
const u32 inverted_mask = ~mask;
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
}
|
||||
else
|
||||
{
|
||||
ARM64Reg WB = gpr.GetReg();
|
||||
MOVZ(WB, imm);
|
||||
BFI(WA, WB, shift, 4);
|
||||
gpr.Unlock(WB);
|
||||
}
|
||||
auto WA = gpr.GetScopedReg();
|
||||
|
||||
if ((mask & (FPSCR_FEX | FPSCR_VX | FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
gpr.Unlock(WA);
|
||||
if (imm == 0xF)
|
||||
{
|
||||
ORR(WA, WA, LogicalImm(mask, GPRSize::B32));
|
||||
}
|
||||
else if (imm == 0x0)
|
||||
{
|
||||
const u32 inverted_mask = ~mask;
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
}
|
||||
else
|
||||
{
|
||||
auto WB = gpr.GetScopedReg();
|
||||
MOVZ(WB, imm);
|
||||
BFI(WA, WB, shift, 4);
|
||||
}
|
||||
|
||||
if ((mask & (FPSCR_FEX | FPSCR_VX | FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
}
|
||||
|
||||
// Field 7 contains NI and RN.
|
||||
if (inst.CRFD == 7)
|
||||
@ -936,49 +907,43 @@ void JitArm64::mtfsfx(UGeckoInstruction inst)
|
||||
if (mask == 0xFFFFFFFF)
|
||||
{
|
||||
ARM64Reg VB = fpr.R(inst.FB, RegType::LowerPair);
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
auto WA = gpr.GetScopedReg();
|
||||
|
||||
m_float_emit.FMOV(WA, EncodeRegToSingle(VB));
|
||||
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
gpr.Unlock(WA);
|
||||
}
|
||||
else if (mask != 0)
|
||||
{
|
||||
ARM64Reg VB = fpr.R(inst.FB, RegType::LowerPair);
|
||||
ARM64Reg WA = gpr.GetReg();
|
||||
ARM64Reg WB = gpr.GetReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
m_float_emit.FMOV(WB, EncodeRegToSingle(VB));
|
||||
|
||||
if (LogicalImm imm = LogicalImm(mask, GPRSize::B32))
|
||||
auto WA = gpr.GetScopedReg();
|
||||
{
|
||||
const u32 inverted_mask = ~mask;
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
AND(WB, WB, imm);
|
||||
auto WB = gpr.GetScopedReg();
|
||||
|
||||
LDR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
m_float_emit.FMOV(WB, EncodeRegToSingle(VB));
|
||||
|
||||
if (LogicalImm imm = LogicalImm(mask, GPRSize::B32))
|
||||
{
|
||||
const u32 inverted_mask = ~mask;
|
||||
AND(WA, WA, LogicalImm(inverted_mask, GPRSize::B32));
|
||||
AND(WB, WB, imm);
|
||||
}
|
||||
else
|
||||
{
|
||||
auto WC = gpr.GetScopedReg();
|
||||
|
||||
MOVI2R(WC, mask);
|
||||
BIC(WA, WA, WC);
|
||||
AND(WB, WB, WC);
|
||||
}
|
||||
ORR(WA, WA, WB);
|
||||
}
|
||||
else
|
||||
{
|
||||
ARM64Reg WC = gpr.GetReg();
|
||||
|
||||
MOVI2R(WC, mask);
|
||||
BIC(WA, WA, WC);
|
||||
AND(WB, WB, WC);
|
||||
|
||||
gpr.Unlock(WC);
|
||||
}
|
||||
ORR(WA, WA, WB);
|
||||
|
||||
gpr.Unlock(WB);
|
||||
|
||||
if ((mask & (FPSCR_FEX | FPSCR_VX | FPSCR_ANY_X | FPSCR_ANY_E)) != 0)
|
||||
UpdateFPExceptionSummary(WA);
|
||||
STR(IndexType::Unsigned, WA, PPC_REG, PPCSTATE_OFF(fpscr));
|
||||
|
||||
gpr.Unlock(WA);
|
||||
}
|
||||
|
||||
if (inst.FM & 1)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user