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Move MOVBE wrappers directly into XEmitter class
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@ -890,6 +890,33 @@ void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, OpArg arg)
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void XEmitter::MOVBE(int bits, X64Reg dest, const OpArg& src) {WriteMOVBE(bits, 0xF0, dest, src);}
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void XEmitter::MOVBE(int bits, const OpArg& dest, X64Reg src) {WriteMOVBE(bits, 0xF1, src, dest);}
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void XEmitter::LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src)
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, dst, src);
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}
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else
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{
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MOV(size, R(dst), src);
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BSWAP(size, dst);
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}
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}
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void XEmitter::SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src)
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, dst, src);
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}
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else
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{
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BSWAP(size, src);
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MOV(size, dst, R(src));
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}
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}
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void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
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{
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_assert_msg_(DYNA_REC, !src.IsImm(), "LEA - Imm argument");
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@ -479,6 +479,8 @@ public:
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// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
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void MOVBE(int bits, X64Reg dest, const OpArg& src);
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void MOVBE(int bits, const OpArg& dest, X64Reg src);
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void LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src);
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void SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src);
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// Available only on AMD >= Phenom or Intel >= Haswell
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void LZCNT(int bits, X64Reg dest, OpArg src);
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