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PixelShaderGen: Cleanups.
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@ -531,27 +531,7 @@ void GeneratePixelShader(T& out, DSTALPHA_MODE dstAlphaMode, API_TYPE ApiType, u
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unsigned int texcoord = bpmem.tevindref.getTexCoord(i);
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unsigned int texmap = bpmem.tevindref.getTexMap(i);
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/// TODO: Cleanup...
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if (i == 0)
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{
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uid_data.tevindref.bc0 = texcoord;
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uid_data.tevindref.bi0 = texmap;
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}
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else if (i == 1)
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{
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uid_data.tevindref.bc1 = texcoord;
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uid_data.tevindref.bi1 = texmap;
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}
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else if (i == 2)
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{
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uid_data.tevindref.bc3 = texcoord;
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uid_data.tevindref.bi2 = texmap;
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}
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else
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{
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uid_data.tevindref.bc4 = texcoord;
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uid_data.tevindref.bi4 = texmap;
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}
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uid_data.tevindref.SetValues(i, texcoord, texmap);
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if (texcoord < numTexgen)
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{
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out.SetConstantsUsed(C_INDTEXSCALE+i/2,C_INDTEXSCALE+i/2);
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@ -585,11 +565,8 @@ void GeneratePixelShader(T& out, DSTALPHA_MODE dstAlphaMode, API_TYPE ApiType, u
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{
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// The results of the last texenv stage are put onto the screen,
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// regardless of the used destination register
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uid_data.combiners[numStages-1].colorC.dest = bpmem.combiners[numStages-1].colorC.dest; // TODO: These probably don't need to be set anymore here...
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uid_data.combiners[numStages-1].alphaC.dest = bpmem.combiners[numStages-1].alphaC.dest;
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if(bpmem.combiners[numStages - 1].colorC.dest != 0)
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{
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/// uid_data.combiners[numStages-1].colorC.dest = bpmem.combiners[numStages-1].colorC.dest;
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bool retrieveFromAuxRegister = !RegisterStates[bpmem.combiners[numStages - 1].colorC.dest].ColorNeedOverflowControl && RegisterStates[bpmem.combiners[numStages - 1].colorC.dest].AuxStored;
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out.Write("\tprev.rgb = %s%s;\n", retrieveFromAuxRegister ? "c" : "" , tevCOutputTable[bpmem.combiners[numStages - 1].colorC.dest]);
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RegisterStates[0].ColorNeedOverflowControl = RegisterStates[bpmem.combiners[numStages - 1].colorC.dest].ColorNeedOverflowControl;
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@ -741,9 +718,9 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
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else uid_data.tevorders_n_texcoord2 |= texcoord << (3 * n - 24);
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if (bHasIndStage)
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{
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uid_data.tevind_n_bs |= bpmem.tevind[n].bs << (2*n);
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uid_data.tevind_n_bt |= bpmem.tevind[n].bt << (2*n);
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uid_data.tevind_n_fmt |= bpmem.tevind[n].fmt << (2*n);
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uid_data.tevind_n.bs |= bpmem.tevind[n].bs << (2*n);
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uid_data.tevind_n.bt |= bpmem.tevind[n].bt << (2*n);
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uid_data.tevind_n.fmt |= bpmem.tevind[n].fmt << (2*n);
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out.Write("// indirect op\n");
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// perform the indirect op on the incoming regular coordinates using indtex%d as the offset coords
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@ -758,14 +735,12 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
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out.Write("float3 indtevcrd%d = indtex%d * %s;\n", n, bpmem.tevind[n].bt, tevIndFmtScale[bpmem.tevind[n].fmt]);
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// bias
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if (n < 8) { uid_data.tevind_n_bias1 |= bpmem.tevind[n].bias << (3*n); } /// XXX: brackets?
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else uid_data.tevind_n_bias2 |= bpmem.tevind[n].bias << (3*n - 24);
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uid_data.tevind_n.Set_bias(n, bpmem.tevind[n].bias);
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if (bpmem.tevind[n].bias != ITB_NONE )
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out.Write("indtevcrd%d.%s += %s;\n", n, tevIndBiasField[bpmem.tevind[n].bias], tevIndBiasAdd[bpmem.tevind[n].fmt]);
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// multiply by offset matrix and scale
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if (n < 8) { uid_data.tevind_n_mid1 |= bpmem.tevind[n].mid << (4*n); } /// XXX: brackets?
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else uid_data.tevind_n_mid2 |= bpmem.tevind[n].mid << (4*n - 32);
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uid_data.tevind_n.Set_mid(n, bpmem.tevind[n].mid);
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if (bpmem.tevind[n].mid != 0)
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{
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if (bpmem.tevind[n].mid <= 3)
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@ -798,13 +773,9 @@ static void WriteStage(T& out, pixel_shader_uid_data& uid_data, int n, API_TYPE
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// ---------
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// Wrapping
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// ---------
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if (n < 8) { uid_data.tevind_n_sw1 |= bpmem.tevind[n].sw << (3 * n); }
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else uid_data.tevind_n_sw2 |= bpmem.tevind[n].sw << (3 * n - 24);
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if (n < 8) { uid_data.tevind_n_tw1 |= bpmem.tevind[n].tw << (3 * n); }
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else uid_data.tevind_n_tw2 |= bpmem.tevind[n].tw << (3 * n - 24);
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uid_data.tevind_n_fb_addprev |= bpmem.tevind[n].fb_addprev << n;
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uid_data.tevind_n.Set_sw(n, bpmem.tevind[n].sw);
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uid_data.tevind_n.Set_tw(n, bpmem.tevind[n].tw);
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uid_data.tevind_n.fb_addprev |= bpmem.tevind[n].fb_addprev << n;
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// wrap S
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if (bpmem.tevind[n].sw == ITW_OFF)
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@ -99,23 +99,54 @@ struct pixel_shader_uid_data
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u32 bc3 : 3;
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u32 bi4 : 3;
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u32 bc4 : 3;
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void SetValues(int index, u32 texcoord, u32 texmap)
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{
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if (index == 0) { bc0 = texcoord; bi0 = texmap; }
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else if (index == 1) { bc1 = texcoord; bi1 = texmap; }
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else if (index == 2) { bc3 = texcoord; bi2 = texmap; }
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else if (index == 3) { bc4 = texcoord; bi4 = texmap; }
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}
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} tevindref;
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u32 tevorders_n_texcoord1 : 24; // 8 x 3 bit
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u32 tevorders_n_texcoord2 : 24; // 8 x 3 bit
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u32 tevind_n_sw1 : 24; // 8 x 3 bit
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u32 tevind_n_sw2 : 24; // 8 x 3 bit
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u32 tevind_n_tw1 : 24; // 8 x 3 bit
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u32 tevind_n_tw2 : 24; // 8 x 3 bit
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u32 tevind_n_fb_addprev : 16; // 16 x 1 bit
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struct
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{
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u32 sw1 : 24; // 8 x 3 bit
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u32 sw2 : 24; // 8 x 3 bit
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u32 tw1 : 24; // 8 x 3 bit
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u32 tw2 : 24; // 8 x 3 bit
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u32 fb_addprev : 16; // 16 x 1 bit
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u32 bs : 32; // 16 x 2 bit
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u32 fmt : 32; // 16 x 2 bit
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u32 bt : 32; // 16 x 2 bit
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u32 bias1 : 24; // 8 x 3 bit
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u32 bias2 : 24; // 8 x 3 bit
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u32 mid1 : 32; // 8 x 4 bit
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u32 mid2 : 32; // 8 x 4 bit
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u32 tevind_n_bs : 32; // 16 x 2 bit
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u32 tevind_n_fmt : 32; // 16 x 2 bit
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u32 tevind_n_bt : 32; // 16 x 2 bit
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u32 tevind_n_bias1 : 24; // 8 x 3 bit
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u32 tevind_n_bias2 : 24; // 8 x 3 bit
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u32 tevind_n_mid1 : 32; // 8 x 4 bit
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u32 tevind_n_mid2 : 32; // 8 x 4 bit
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// NOTE: These assume that the affected bits are zero before calling
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void Set_sw(int index, u32 val)
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{
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if (index < 8) sw1 |= val << (3*index);
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else sw2 |= val << (3*index - 24);
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}
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void Set_tw(int index, u32 val)
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{
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if (index < 8) tw1 |= val << (3*index);
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else tw2 |= val << (3*index - 24);
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}
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void Set_bias(int index, u32 val)
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{
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if (index < 8) bias1 |= val << (3*index);
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else bias2 |= val << (3*index - 24);
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}
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void Set_mid(int index, u32 val)
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{
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if (index < 8) mid1 |= val << (4*index);
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else mid2 |= val << (4*index - 32);
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}
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} tevind_n;
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u32 tevksel_n_swap : 32; // 8 x 2 bit (swap1) + 8 x 2 bit (swap2)
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struct
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