Commit Graph

33831 Commits

Author SHA1 Message Date
Léo Lam
dcc313fd96
Merge pull request #9346 from Sintendo/jitarm64ub
JitArm64: Fix signed bitwise left shift UB
2020-12-26 11:56:33 +01:00
Léo Lam
d2f9991b0f
Merge pull request #9360 from Minty-Meeo/osreport-split
Split OSREPORT logging type
2020-12-26 11:41:18 +01:00
Sintendo
67d2fa11f1 Jit64: srawx - Handle constant zero input
Shifting zero by any amount always gives zero.

Before:
41 B9 00 00 00 00    mov         r9d,0
41 8B CF             mov         ecx,r15d
49 C1 E1 20          shl         r9,20h
49 D3 F9             sar         r9,cl
49 C1 E9 20          shr         r9,20h

After:
Nothing, register is set to constant zero.

Before:
41 B8 00 00 00 00    mov         r8d,0
41 8B CF             mov         ecx,r15d
49 C1 E0 20          shl         r8,20h
49 D3 F8             sar         r8,cl
41 8B C0             mov         eax,r8d
49 C1 E8 20          shr         r8,20h
44 85 C0             test        eax,r8d
0F 95 45 58          setne       byte ptr [rbp+58h]

After:
C6 45 58 00          mov         byte ptr [rbp+58h],0

Occurs a bunch of times in Super Mario Sunshine. Since this is an
arithmetic shift a similar optimization can be done for constant -1
(0xFFFFFFFF), but I couldn't find any game where this happens.
2020-12-25 19:30:51 +01:00
Sintendo
10d65519f9 Jit64: slwx - Handle constant zero input
Shifting zero by any amount always gives zero.

Before:
41 BF 00 00 00 00    mov         r15d,0
8B CF                mov         ecx,edi
49 D3 E7             shl         r15,cl
45 8B FF             mov         r15d,r15d

After:
Nothing, register is set to constant zero.

All games I've tried hit this optimization on launch. In Soul Calibur II
it occurs very frequently during gameplay.
2020-12-25 19:30:51 +01:00
Sintendo
1a52fdf7e3 Jit64: rlwnmx - Optimize rotate by constant
Only removes the scratch register and a MOV, but hey.

Before:
B9 02 00 00 00       mov         ecx,2
41 8B F5             mov         esi,r13d
D3 C6                rol         esi,cl
83 E6 01             and         esi,1

After:
41 8B F5             mov         esi,r13d
C1 C6 02             rol         esi,2
83 E6 01             and         esi,1
2020-12-25 19:30:51 +01:00
Sintendo
cb70d5ee4f Jit64: srawix - Handle constant input register
Much like we did for srawx. This was already implemented on JitArm64.

Before:
B8 00 00 00 00       mov         eax,0
8B F0                mov         esi,eax
C1 E8 1F             shr         eax,1Fh
23 C6                and         eax,esi
D1 FE                sar         esi,1
88 45 58             mov         byte ptr [rbp+58h],al

After:
C6 45 58 00          mov         byte ptr [rbp+58h],0
2020-12-25 19:30:51 +01:00
Sintendo
8ac40162da Jit64: srawx - Handle constant input registers
If both input registers hold known values at compile time, we can just
calculate the result on the spot.

Code has mostly been copied from JitArm64 where it had already been implemented.

Before:
BF FF FF FF FF       mov         edi,0FFFFFFFFh
8B C7                mov         eax,edi
C1 FF 10             sar         edi,10h
C1 E0 10             shl         eax,10h
85 F8                test        eax,edi
0F 95 45 58          setne       byte ptr [rbp+58h]

After:
C6 45 58 01          mov         byte ptr [rbp+58h],1
2020-12-25 19:30:51 +01:00
Sintendo
b968120f8a Jit64: srawx - Optimize shift by constant
More efficient code can be generated if the shift amount is known at
compile time. We can once again take advantage of shifts with the shift
amount in an 8-bit immediate to eliminate ECX as a scratch register,
reducing register pressure and removing the occasional spill. We can
also do 32-bit shifts instead of 64-bit operations.

We recognize four distinct cases:

- The special case where we're dealing with the PowerPC's quirky shift
  amount masking. If the shift amount is a number from 32 to 63, all
  bits are shifted out and the result it either all zeroes or all ones.

Before:
B9 F0 FF FF FF       mov         ecx,0FFFFFFF0h
8B F7                mov         esi,edi
48 C1 E6 20          shl         rsi,20h
48 D3 FE             sar         rsi,cl
8B C6                mov         eax,esi
48 C1 EE 20          shr         rsi,20h
85 F0                test        eax,esi
0F 95 45 58          setne       byte ptr [rbp+58h]

After:
8B F7                mov         esi,edi
C1 FE 1F             sar         esi,1Fh
0F 95 45 58          setne       byte ptr [rbp+58h]

- The shift amount is zero. Not calculation needs to be done, just clear
  the carry flag.

Before:
B9 00 00 00 00       mov         ecx,0
49 C1 E5 20          shl         r13,20h
49 D3 FD             sar         r13,cl
41 8B C5             mov         eax,r13d
49 C1 ED 20          shr         r13,20h
44 85 E8             test        eax,r13d
0F 95 45 58          setne       byte ptr [rbp+58h]

After:
C6 45 58 00          mov         byte ptr [rbp+58h],0

- The carry flag doesn't need to be computed. Just do the arithmetic
  shift.

Before:
B9 02 00 00 00       mov         ecx,2
48 C1 E7 20          shl         rdi,20h
48 D3 FF             sar         rdi,cl
48 C1 EF 20          shr         rdi,20h

After:
C1 FF 02             sar         edi,2

- The carry flag must be computed. In addition to the arithmetic shift,
  we do a shift to the left and and them together to know if any ones
  were shifted out. It's still better than before, because we can do
  32-bit shifts.

Before:
B9 02 00 00 00       mov         ecx,2
49 C1 E5 20          shl         r13,20h
49 D3 FD             sar         r13,cl
41 8B C5             mov         eax,r13d
49 C1 ED 20          shr         r13,20h
44 85 E8             test        eax,r13d
0F 95 45 58          setne       byte ptr [rbp+58h]

After:
41 8B C5             mov         eax,r13d
41 C1 FD 02          sar         r13d,2
C1 E0 1E             shl         eax,1Eh
44 85 E8             test        eax,r13d
0F 95 45 58          setne       byte ptr [rbp+58h]
2020-12-25 19:30:51 +01:00
Sintendo
17dc870847 Jit64: slwx - Optimize shift by constant
More efficient code can be generated if the shift amount is known at
compile time. Similar optimizations were present in JitArm64 already,
but were missing in Jit64.

- By using an 8-bit immediate we can eliminate the need for ECX as a
  scratch register, thereby reducing register pressure and occasionally
  eliminating a spill.

Before:
B9 18 00 00 00       mov         ecx,18h
41 8B F7             mov         esi,r15d
48 D3 E6             shl         rsi,cl
8B F6                mov         esi,esi

After:
41 8B CF             mov         ecx,r15d
C1 E1 18             shl         ecx,18h

- PowerPC has strange shift amount masking behavior which is emulated
  using 64-bit shifts, even though we only care about a 32-bit result.
  If the shift amount is known, we can handle this special case
  separately, and use 32-bit shift instructions otherwise. We also no
  longer need to clear the upper 32 bits of the register.

Before:
BE F8 FF FF FF       mov         esi,0FFFFFFF8h
8B CE                mov         ecx,esi
41 8B F4             mov         esi,r12d
48 D3 E6             shl         rsi,cl
8B F6                mov         esi,esi

After:
Nothing, register is set to constant zero.

- A shift by zero becomes a simple MOV.

Before:
BE 00 00 00 00       mov         esi,0
8B CE                mov         ecx,esi
41 8B F3             mov         esi,r11d
48 D3 E6             shl         rsi,cl
8B F6                mov         esi,esi

After:
41 8B FB             mov         edi,r11d
2020-12-25 19:30:51 +01:00
Sintendo
17db359979 Jit64: srwx - Optimize shift by constant
More efficient code can be generated if the shift amount is known at
compile time. Similar optimizations were present in JitArm64 already,
but were missing in Jit64.

- By using an 8-bit immediate we can eliminate the need for ECX as a
  scratch register, thereby reducing register pressure and occasionally
  eliminating a spill.

Before:
B9 18 00 00 00       mov         ecx,18h
45 8B C1             mov         r8d,r9d
49 D3 E8             shr         r8,cl

After:
45 8B C1             mov         r8d,r9d
41 C1 E8 18          shr         r8d,18h

- PowerPC has strange shift amount masking behavior which is emulated
  using 64-bit shifts, even though we only care about a 32-bit result.
  If the shift amount is known, we can handle this special case
  separately, and use 32-bit shift instructions otherwise.

Before:
B9 F8 FF FF FF       mov         ecx,0FFFFFFF8h
45 8B C1             mov         r8d,r9d
49 D3 E8             shr         r8,cl

After:
Nothing, register is set to constant zero.

- A shift by zero becomes a simple MOV.

Before:
B9 00 00 00 00       mov         ecx,0
45 8B C1             mov         r8d,r9d
49 D3 E8             shr         r8,cl

After:
45 8B C1             mov         r8d,r9d
2020-12-25 19:30:51 +01:00
Sintendo
2e4e2ad1ff Jit64: subfic - Handle constants
Occurs surprisingly often. Prevents generating silly code like this:

BE 03 00 00 00       mov         esi,3
83 EE 08             sub         esi,8
0F 93 45 58          setae       byte ptr [rbp+58h]
2020-12-25 19:30:51 +01:00
Minty-Meeo
b430d66cdc Split OSREPORT logging type
The enumerated LOG_TYPE "OSREPORT" is currently used in both EXI_DeviceIPL.cpp and HLE_OS.cpp.  In many games, the multitude of game functions detected by HLE_OS.cpp for OSREPORT logging results in poor log readability.  This Pull Request remedies that by adding a new enumerated LOG_TYPE "OSREPORT_HLE" for log usage in HLE_OS.cpp.

In the future, further changing how logging in HLE_OS.cpp works may be desirable.  As it is, game functions are detected that send a single character to the log.  This is a major source of poor readability.
2020-12-24 23:38:59 -06:00
Léo Lam
0aadb9fd7b
Build the gdbstub by default
While the gdbstub is somewhat broken at the moment, building it by
default should keep us from breaking the build (which has happened
several times in the past: #2614, #5904, #8262).

It isn't very intrusive and it does nothing unless it is enabled
in the config file.
2020-12-25 01:21:36 +01:00
Léo Lam
ae187818f5
PowerPC: Fix GDBStub build 2020-12-25 01:15:31 +01:00
Léo Lam
6ddf69d094
Merge pull request #9353 from MaddTheSane/patch-1
CMake: Apple Silicon detection
2020-12-24 22:50:27 +01:00
C.W. Betts
1100a31407 CMake: Apple Silicon detection
CMake's CMAKE_SYSTEM_PROCESSOR call returns "arm64" on Apple Silicon. This patch makes sure that arm64 and aarch64 are treated as the same architecture.
2020-12-24 14:34:04 -07:00
LC
26c097ebfc
Merge pull request #8867 from iwubcode/freelook_controller
Make Free Look a proper controller, move to separate UI
2020-12-24 15:10:17 -05:00
iwubcode
c7b24d6213 VideoCommon: Update active config when we check for config changes, this ensures Free Look settings are copied at the start of the frame. Also update the camera's controller type at this time 2020-12-24 13:51:46 -06:00
iwubcode
a893c25b01 Core: Refresh the Free Look configuration when Free Look is initialized, ensuring that the configuration updates appropriately with any changes 2020-12-24 13:49:25 -06:00
iwubcode
b4c41adac4 Core: Only respond to Free Look controller buttons when the camera is active 2020-12-24 13:49:25 -06:00
iwubcode
b9d9b27a81 DolphinQt: Only trigger Free Look mouse movement when the Free Look camera is active 2020-12-24 13:49:25 -06:00
iwubcode
bcf63c463b VideoCommon: Add 'Active' state to FreelookCamera to future proof if we ever add multiple cameras 2020-12-24 13:49:25 -06:00
iwubcode
a37fd8c5d9 VideoCommon: Update Free Look camera with settings change... 2020-12-24 13:49:25 -06:00
iwubcode
670f34af60 Core: Update state to account for save system change 2020-12-24 13:49:25 -06:00
iwubcode
9bd4e0939e DolphinQt: Update mapping window device to use expanding size policy 2020-12-24 13:49:25 -06:00
iwubcode
9a744ab25b DolphinQt: Move Free Look out of Graphics/Hotkey and into its own configuration window. Launched from a new menu option - "Free Look Settings". The HotKeyScheduler still calls the Free Look functionality to reduce the total number of threads 2020-12-24 13:49:25 -06:00
iwubcode
9ac6090c9a Core: Add Free Look controllers that are initialized at boot 2020-12-24 13:49:25 -06:00
iwubcode
27acba620c Core: Add new Free Look settings and config 2020-12-24 13:49:25 -06:00
iwubcode
f6ab9a9b6f Core / VideoCommon: Remove old Free Look config 2020-12-24 13:49:25 -06:00
iwubcode
e7ac095ba1 HotkeyManager: Remove Free Look functionality in preparation for replacement 2020-12-24 13:48:38 -06:00
iwubcode
d5bc209eb6 VideoCommon: Change 'Zoom' to 'MoveForward' since it really isn't a zoom 2020-12-24 13:48:38 -06:00
iwubcode
cb6ae6a4b1 VideoCommon: Add speed to Free Look camera 2020-12-24 13:48:38 -06:00
LC
d61c64684b
Merge pull request #9357 from JosJuice/android-one-settings-entrypoint
Android: Only have one settings entrypoint per activity/dialog
2020-12-24 12:46:43 -05:00
LC
464bc80482
Merge pull request #9356 from JosJuice/android-save-ingame-change
Android: Correctly save in-game settings changes to disk
2020-12-24 12:45:09 -05:00
JosJuice
8c723d0584 Android: Only have one settings entrypoint per activity/dialog
Basically, instead of having one button for config, one button
for graphics settings and so on, we now have just one settings
button which takes you to a screen where you pick between
config/graphics/GameCube controllers/Wii Remotes.

The main reason I want to do this is because people still have
trouble finding Overlay Controls in the "new" in-game menu.
Typically (depending on the screen size and the length of the
game name), the scrollable part of the menu can fit 4 items,
and merging Config and Graphics Settings into one item would
move Overlay Controls from 5th place to 4th place (assuming the
user doesn't have savestates enabled), which makes it findable
even for users who don't realize the menu can be scrolled.

The dialog that's shown when long pressing a game in the game
list is also shortened. While not a pressing matter, I think
it was getting a bit long.

An additional reason to do this is because we probably will
want to make it possible to edit the controller settings
from the in-game menu at some point in the future. With the
old approach, this would require us to dedicate a whopping 4
menu items just for settings (not including Overlay Controls),
which I think is excessive.
2020-12-24 16:48:20 +01:00
JosJuice
8f475371b9 JitArm64: Call UpdatePerformanceMonitor 2020-12-24 16:23:24 +01:00
JosJuice
6f05c40013 Android: Correctly save in-game settings changes to disk 2020-12-24 13:37:33 +01:00
JosJuice
8c0f32e6be Interpreter: Call UpdatePerformanceMonitor 2020-12-23 17:34:47 +01:00
JosJuice
2dcd0b248f CachedInterpreter: Call UpdatePerformanceMonitor 2020-12-23 17:34:32 +01:00
JosJuice
f8f3548ca9 CoreTiming: Call UpdatePerformanceMonitor on idle 2020-12-23 17:34:02 +01:00
Markus Wick
1d489b3fd5
Merge pull request #9347 from JosJuice/fpr-utilization
Jit64: Fix FPURegCache::GetRegUtilization
2020-12-21 18:37:03 +01:00
JosJuice
9460467e7c Jit64: Fix FPURegCache::GetRegUtilization
This performance bug was probably a simple copy-paste error.
(The function was identical to GPRRegCache::GetRegUtilization.)
2020-12-21 18:02:43 +01:00
Sintendo
567357e12d JitArm64: srawix - Fix undefined behavior
Signed bitwise left shift invokes UB when shifting a negative value.
2020-12-21 11:05:22 +01:00
Sintendo
97eb616719 JitArm64: srawx - Fix undefined behavior
Signed bitwise left shift invokes UB when shifting a negative value.
2020-12-21 11:01:42 +01:00
LC
4c8ccc63b5
Merge pull request #9345 from MerryMage/analytics
Analytics: Add rarer OSes to analytics
2020-12-20 18:55:34 -05:00
LC
7c81f0256c
Merge pull request #9344 from MerryMage/HW_PHYSMEM64
MemoryUtil: Use HW_PHYSMEM64 sysctl in MemPhysical
2020-12-20 18:53:46 -05:00
MerryMage
d109451ad5 Analytics: Add rarer OSes to analytics 2020-12-20 22:32:07 +00:00
MerryMage
29fceeb37f MemoryUtil: Use HW_PHYSMEM64 sysctl in MemPhysical
HW_PHYSMEM is deprecated on OpenBSD and only supplies a 32-bit value on NetBSD
2020-12-20 22:25:36 +00:00
JosJuice
c582fb098d
Merge pull request #9342 from lioncash/system
Core: Add initial System class
2020-12-20 13:57:15 +01:00
JosJuice
399ede37a6 Android: Catch all exceptions in ContentHandler 2020-12-20 13:24:54 +01:00