2017-01-22 12:34:59 -07:00
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/*
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Copyright 2016-2017 StapleButter
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "NDS.h"
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#include "NDSCart.h"
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2017-01-31 09:34:17 -07:00
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namespace NDSCart_SRAM
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{
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u8* SRAM;
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u32 SRAMLength;
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2017-02-03 08:57:31 -07:00
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char SRAMPath[256];
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void (*WriteFunc)(u8 val, bool islast);
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u32 Discover_MemoryType;
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u32 Discover_Likeliness;
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u8* Discover_Buffer;
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u32 Discover_DataPos;
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2017-01-31 09:34:17 -07:00
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u32 Hold;
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u8 CurCmd;
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u32 DataPos;
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u8 Data;
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u8 StatusReg;
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u32 Addr;
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2017-02-03 08:57:31 -07:00
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void Write_Null(u8 val, bool islast);
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void Write_EEPROMTiny(u8 val, bool islast);
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void Write_EEPROM(u8 val, bool islast);
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void Write_Flash(u8 val, bool islast);
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void Write_Discover(u8 val, bool islast);
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2017-02-07 14:23:46 -07:00
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bool Init()
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2017-01-31 09:34:17 -07:00
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{
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SRAM = NULL;
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2017-02-05 09:45:17 -07:00
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Discover_Buffer = NULL;
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2017-02-07 14:23:46 -07:00
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return true;
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}
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void DeInit()
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{
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if (SRAM) delete[] SRAM;
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if (Discover_Buffer) delete[] Discover_Buffer;
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2017-01-31 09:34:17 -07:00
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}
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void Reset()
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2017-02-03 08:57:31 -07:00
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{
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2017-03-29 10:59:20 -06:00
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if (SRAM) delete[] SRAM;
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if (Discover_Buffer) delete[] Discover_Buffer;
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SRAM = NULL;
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Discover_Buffer = NULL;
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2017-02-03 08:57:31 -07:00
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}
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void LoadSave(char* path)
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2017-01-31 09:34:17 -07:00
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{
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if (SRAM) delete[] SRAM;
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2017-02-05 09:45:17 -07:00
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if (Discover_Buffer) delete[] Discover_Buffer;
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2017-01-31 09:34:17 -07:00
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2017-02-07 14:23:46 -07:00
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Discover_Buffer = NULL;
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2017-02-03 08:57:31 -07:00
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strncpy(SRAMPath, path, 255);
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SRAMPath[255] = '\0';
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FILE* f = fopen(path, "rb");
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2017-01-31 09:34:17 -07:00
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if (f)
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{
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fseek(f, 0, SEEK_END);
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SRAMLength = (u32)ftell(f);
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SRAM = new u8[SRAMLength];
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fseek(f, 0, SEEK_SET);
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fread(SRAM, SRAMLength, 1, f);
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fclose(f);
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switch (SRAMLength)
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{
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2017-02-03 08:57:31 -07:00
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case 512: WriteFunc = Write_EEPROMTiny; break;
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case 8192:
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case 65536: WriteFunc = Write_EEPROM; break;
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case 256*1024:
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case 512*1024:
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case 1024*1024:
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case 8192*1024: WriteFunc = Write_Flash; break;
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2017-01-31 09:34:17 -07:00
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default:
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printf("!! BAD SAVE LENGTH %d\n", SRAMLength);
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2017-02-03 08:57:31 -07:00
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WriteFunc = Write_Null;
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2017-01-31 09:34:17 -07:00
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break;
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}
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}
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else
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{
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SRAMLength = 0;
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2017-02-03 08:57:31 -07:00
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WriteFunc = Write_Discover;
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Discover_MemoryType = 2;
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Discover_Likeliness = 0;
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Discover_DataPos = 0;
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Discover_Buffer = new u8[256*1024];
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memset(Discover_Buffer, 0, 256*1024);
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2017-01-31 09:34:17 -07:00
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}
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Hold = 0;
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CurCmd = 0;
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Data = 0;
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StatusReg = 0x00;
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}
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u8 Read()
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{
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return Data;
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}
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2017-02-03 08:57:31 -07:00
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void SetMemoryType()
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{
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switch (Discover_MemoryType)
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{
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case 1:
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printf("Save memory type: EEPROM 4k\n");
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WriteFunc = Write_EEPROMTiny;
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SRAMLength = 512;
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break;
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case 2:
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printf("Save memory type: EEPROM 64k\n");
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WriteFunc = Write_EEPROM;
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SRAMLength = 8192;
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break;
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case 3:
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printf("Save memory type: EEPROM 512k\n");
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WriteFunc = Write_EEPROM;
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SRAMLength = 65536;
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break;
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case 4:
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printf("Save memory type: Flash. Hope the size is 256K.\n");
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WriteFunc = Write_Flash;
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SRAMLength = 256*1024;
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break;
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case 5:
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printf("Save memory type: ...something else\n");
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WriteFunc = Write_Null;
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SRAMLength = 0;
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break;
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}
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if (!SRAMLength)
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return;
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SRAM = new u8[SRAMLength];
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// replay writes that occured during discovery
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u8 prev_cmd = CurCmd;
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u32 pos = 0;
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while (pos < 256*1024)
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{
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u32 len = *(u32*)&Discover_Buffer[pos];
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pos += 4;
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if (len == 0) break;
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CurCmd = Discover_Buffer[pos++];
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DataPos = 0;
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Addr = 0;
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Data = 0;
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for (u32 i = 1; i < len; i++)
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{
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WriteFunc(Discover_Buffer[pos++], (i==(len-1)));
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DataPos++;
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}
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}
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CurCmd = prev_cmd;
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2017-02-05 09:45:17 -07:00
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delete[] Discover_Buffer;
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2017-03-24 13:53:01 -06:00
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Discover_Buffer = NULL;
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2017-02-03 08:57:31 -07:00
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}
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void Write_Discover(u8 val, bool islast)
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{
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// attempt at autodetecting the type of save memory.
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// we basically hope the game will be nice and clear whole pages of memory.
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if (CurCmd == 0x03 || CurCmd == 0x0B)
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{
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if (Discover_Likeliness)
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{
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// apply. and pray.
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SetMemoryType();
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DataPos = 0;
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Addr = 0;
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Data = 0;
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return WriteFunc(val, islast);
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}
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else
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{
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Data = 0;
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return;
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}
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}
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if (CurCmd == 0x02 || CurCmd == 0x0A)
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{
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if (DataPos == 0)
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Discover_Buffer[Discover_DataPos + 4] = CurCmd;
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Discover_Buffer[Discover_DataPos + 5 + DataPos] = val;
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if (islast)
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{
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u32 len = DataPos+1;
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*(u32*)&Discover_Buffer[Discover_DataPos] = len+1;
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Discover_DataPos += 5+len;
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if (Discover_Likeliness <= len)
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{
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Discover_Likeliness = len;
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if (len > 3+256) // bigger Flash, FRAM, whatever
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{
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Discover_MemoryType = 5;
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}
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else if (len > 2+128) // Flash
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{
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Discover_MemoryType = 4;
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}
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else if (len > 2+32) // EEPROM 512k
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{
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Discover_MemoryType = 3;
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}
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else if (len > 1+16 || (len != 1+16 && CurCmd != 0x0A)) // EEPROM 64k
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{
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Discover_MemoryType = 2;
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}
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else // EEPROM 4k
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{
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Discover_MemoryType = 1;
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}
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}
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printf("discover: type=%d likeliness=%d\n", Discover_MemoryType, Discover_Likeliness);
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}
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}
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}
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void Write_Null(u8 val, bool islast) {}
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void Write_EEPROMTiny(u8 val, bool islast)
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{
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2017-03-23 16:47:55 -06:00
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switch (CurCmd)
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{
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case 0x02:
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case 0x0A:
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if (DataPos < 1)
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{
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Addr = val;
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Data = 0;
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}
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else
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{
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2017-04-10 17:21:35 -06:00
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SRAM[(Addr + ((CurCmd==0x0A)?0x100:0)) & 0x1FF] = val;
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2017-03-23 16:47:55 -06:00
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Addr++;
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}
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break;
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case 0x03:
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case 0x0B:
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if (DataPos < 1)
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{
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Addr = val;
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Data = 0;
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}
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else
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{
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2017-04-10 17:21:35 -06:00
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Data = SRAM[(Addr + ((CurCmd==0x0B)?0x100:0)) & 0x1FF];
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2017-03-23 16:47:55 -06:00
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Addr++;
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}
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break;
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case 0x9F:
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Data = 0xFF;
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break;
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default:
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if (DataPos==0)
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printf("unknown tiny EEPROM save command %02X\n", CurCmd);
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break;
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}
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2017-02-03 08:57:31 -07:00
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}
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void Write_EEPROM(u8 val, bool islast)
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{
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switch (CurCmd)
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{
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case 0x02:
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if (DataPos < 2)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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2017-02-05 09:45:17 -07:00
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SRAM[Addr & (SRAMLength-1)] = val;
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2017-02-03 08:57:31 -07:00
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Addr++;
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}
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break;
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case 0x03:
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if (DataPos < 2)
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{
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Addr <<= 8;
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Addr |= val;
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Data = 0;
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}
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else
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{
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2017-02-05 09:45:17 -07:00
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Data = SRAM[Addr & (SRAMLength-1)];
|
2017-02-03 08:57:31 -07:00
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9F:
|
|
|
|
|
Data = 0xFF;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
if (DataPos==0)
|
|
|
|
|
printf("unknown EEPROM save command %02X\n", CurCmd);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Write_Flash(u8 val, bool islast)
|
|
|
|
|
{
|
|
|
|
|
switch (CurCmd)
|
|
|
|
|
{
|
2017-03-29 14:12:53 -06:00
|
|
|
|
case 0x02:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = 0;
|
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2017-02-03 08:57:31 -07:00
|
|
|
|
case 0x03:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2017-03-23 16:55:22 -06:00
|
|
|
|
Data = SRAM[Addr & (SRAMLength-1)];
|
2017-02-03 08:57:31 -07:00
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x0A:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
2017-03-23 16:55:22 -06:00
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = val;
|
2017-02-03 08:57:31 -07:00
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x9F:
|
|
|
|
|
Data = 0xFF;
|
|
|
|
|
break;
|
|
|
|
|
|
2017-03-29 14:12:53 -06:00
|
|
|
|
case 0xD8:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
if (DataPos == 2)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < 0x10000; i++)
|
|
|
|
|
{
|
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = 0;
|
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xDB:
|
|
|
|
|
if (DataPos < 3)
|
|
|
|
|
{
|
|
|
|
|
Addr <<= 8;
|
|
|
|
|
Addr |= val;
|
|
|
|
|
Data = 0;
|
|
|
|
|
}
|
|
|
|
|
if (DataPos == 2)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < 0x100; i++)
|
|
|
|
|
{
|
|
|
|
|
SRAM[Addr & (SRAMLength-1)] = 0;
|
|
|
|
|
Addr++;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2017-02-03 08:57:31 -07:00
|
|
|
|
default:
|
|
|
|
|
if (DataPos==0)
|
|
|
|
|
printf("unknown Flash save command %02X\n", CurCmd);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
void Write(u8 val, u32 hold)
|
|
|
|
|
{
|
2017-02-03 08:57:31 -07:00
|
|
|
|
bool islast = false;
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
if (!hold)
|
|
|
|
|
{
|
2017-02-03 08:57:31 -07:00
|
|
|
|
if (Hold) islast = true;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
Hold = 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (hold && (!Hold))
|
|
|
|
|
{
|
|
|
|
|
CurCmd = val;
|
|
|
|
|
Hold = 1;
|
|
|
|
|
Data = 0;
|
2017-02-03 08:57:31 -07:00
|
|
|
|
DataPos = 0;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
Addr = 0;
|
|
|
|
|
//printf("save SPI command %02X\n", CurCmd);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (CurCmd)
|
|
|
|
|
{
|
2017-04-10 12:56:22 -06:00
|
|
|
|
case 0x00:
|
|
|
|
|
// Pok<6F>mon carts have an IR transceiver thing, and send this
|
|
|
|
|
// to bypass it and access SRAM.
|
|
|
|
|
// TODO: design better
|
|
|
|
|
CurCmd = val;
|
|
|
|
|
break;
|
|
|
|
|
|
2017-02-03 08:57:31 -07:00
|
|
|
|
case 0x02:
|
|
|
|
|
case 0x03:
|
|
|
|
|
case 0x0A:
|
|
|
|
|
case 0x0B:
|
|
|
|
|
case 0x9F:
|
|
|
|
|
WriteFunc(val, islast);
|
|
|
|
|
DataPos++;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x04: // write disable
|
|
|
|
|
StatusReg &= ~(1<<1);
|
|
|
|
|
Data = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x05: // read status reg
|
|
|
|
|
Data = StatusReg;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x06: // write enable
|
|
|
|
|
StatusReg |= (1<<1);
|
|
|
|
|
Data = 0;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2017-04-10 12:56:22 -06:00
|
|
|
|
if (DataPos==0)
|
|
|
|
|
printf("unknown save SPI command %02X %08X\n", CurCmd);
|
2017-01-31 09:34:17 -07:00
|
|
|
|
break;
|
|
|
|
|
}
|
2017-02-03 08:57:31 -07:00
|
|
|
|
|
2017-03-23 16:55:22 -06:00
|
|
|
|
if (islast && (CurCmd == 0x02 || CurCmd == 0x0A) && (SRAMLength > 0))
|
2017-02-03 08:57:31 -07:00
|
|
|
|
{
|
|
|
|
|
FILE* f = fopen(SRAMPath, "wb");
|
|
|
|
|
if (f)
|
|
|
|
|
{
|
|
|
|
|
fwrite(SRAM, SRAMLength, 1, f);
|
|
|
|
|
fclose(f);
|
|
|
|
|
}
|
|
|
|
|
}
|
2017-01-31 09:34:17 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
namespace NDSCart
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
u16 SPICnt;
|
|
|
|
|
u32 ROMCnt;
|
|
|
|
|
|
|
|
|
|
u8 ROMCommand[8];
|
|
|
|
|
u32 ROMDataOut;
|
|
|
|
|
|
|
|
|
|
u8 DataOut[0x4000];
|
|
|
|
|
u32 DataOutPos;
|
|
|
|
|
u32 DataOutLen;
|
|
|
|
|
|
|
|
|
|
bool CartInserted;
|
|
|
|
|
u8* CartROM;
|
|
|
|
|
u32 CartROMSize;
|
|
|
|
|
u32 CartID;
|
2017-01-22 18:26:05 -07:00
|
|
|
|
bool CartIsHomebrew;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
u32 CmdEncMode;
|
|
|
|
|
u32 DataEncMode;
|
|
|
|
|
|
|
|
|
|
u32 Key1_KeyBuf[0x412];
|
|
|
|
|
|
|
|
|
|
u64 Key2_X;
|
|
|
|
|
u64 Key2_Y;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
u32 ByteSwap(u32 val)
|
|
|
|
|
{
|
|
|
|
|
return (val >> 24) | ((val >> 8) & 0xFF00) | ((val << 8) & 0xFF0000) | (val << 24);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_Encrypt(u32* data)
|
|
|
|
|
{
|
|
|
|
|
u32 y = data[0];
|
|
|
|
|
u32 x = data[1];
|
|
|
|
|
u32 z;
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0x0; i <= 0xF; i++)
|
|
|
|
|
{
|
|
|
|
|
z = Key1_KeyBuf[i] ^ x;
|
|
|
|
|
x = Key1_KeyBuf[0x012 + (z >> 24) ];
|
|
|
|
|
x += Key1_KeyBuf[0x112 + ((z >> 16) & 0xFF)];
|
|
|
|
|
x ^= Key1_KeyBuf[0x212 + ((z >> 8) & 0xFF)];
|
|
|
|
|
x += Key1_KeyBuf[0x312 + (z & 0xFF)];
|
|
|
|
|
x ^= y;
|
|
|
|
|
y = z;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
data[0] = x ^ Key1_KeyBuf[0x10];
|
|
|
|
|
data[1] = y ^ Key1_KeyBuf[0x11];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_Decrypt(u32* data)
|
|
|
|
|
{
|
|
|
|
|
u32 y = data[0];
|
|
|
|
|
u32 x = data[1];
|
|
|
|
|
u32 z;
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0x11; i >= 0x2; i--)
|
|
|
|
|
{
|
|
|
|
|
z = Key1_KeyBuf[i] ^ x;
|
|
|
|
|
x = Key1_KeyBuf[0x012 + (z >> 24) ];
|
|
|
|
|
x += Key1_KeyBuf[0x112 + ((z >> 16) & 0xFF)];
|
|
|
|
|
x ^= Key1_KeyBuf[0x212 + ((z >> 8) & 0xFF)];
|
|
|
|
|
x += Key1_KeyBuf[0x312 + (z & 0xFF)];
|
|
|
|
|
x ^= y;
|
|
|
|
|
y = z;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
data[0] = x ^ Key1_KeyBuf[0x1];
|
|
|
|
|
data[1] = y ^ Key1_KeyBuf[0x0];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_ApplyKeycode(u32* keycode, u32 mod)
|
|
|
|
|
{
|
|
|
|
|
Key1_Encrypt(&keycode[1]);
|
|
|
|
|
Key1_Encrypt(&keycode[0]);
|
|
|
|
|
|
|
|
|
|
u32 temp[2] = {0,0};
|
|
|
|
|
|
|
|
|
|
for (u32 i = 0; i <= 0x11; i++)
|
|
|
|
|
{
|
|
|
|
|
Key1_KeyBuf[i] ^= ByteSwap(keycode[i % mod]);
|
|
|
|
|
}
|
|
|
|
|
for (u32 i = 0; i <= 0x410; i+=2)
|
|
|
|
|
{
|
|
|
|
|
Key1_Encrypt(temp);
|
|
|
|
|
Key1_KeyBuf[i ] = temp[1];
|
|
|
|
|
Key1_KeyBuf[i+1] = temp[0];
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Key1_InitKeycode(u32 idcode, u32 level, u32 mod)
|
|
|
|
|
{
|
|
|
|
|
memcpy(Key1_KeyBuf, &NDS::ARM7BIOS[0x30], 0x1048); // hax
|
|
|
|
|
|
|
|
|
|
u32 keycode[3] = {idcode, idcode>>1, idcode<<1};
|
|
|
|
|
if (level >= 1) Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
if (level >= 2) Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
if (level >= 3)
|
|
|
|
|
{
|
|
|
|
|
keycode[1] <<= 1;
|
|
|
|
|
keycode[2] >>= 1;
|
|
|
|
|
Key1_ApplyKeycode(keycode, mod);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void Key2_Encrypt(u8* data, u32 len)
|
|
|
|
|
{
|
|
|
|
|
for (u32 i = 0; i < len; i++)
|
|
|
|
|
{
|
|
|
|
|
Key2_X = (((Key2_X >> 5) ^
|
|
|
|
|
(Key2_X >> 17) ^
|
|
|
|
|
(Key2_X >> 18) ^
|
|
|
|
|
(Key2_X >> 31)) & 0xFF)
|
|
|
|
|
+ (Key2_X << 8);
|
|
|
|
|
Key2_Y = (((Key2_Y >> 5) ^
|
|
|
|
|
(Key2_Y >> 23) ^
|
|
|
|
|
(Key2_Y >> 18) ^
|
|
|
|
|
(Key2_Y >> 31)) & 0xFF)
|
|
|
|
|
+ (Key2_Y << 8);
|
|
|
|
|
|
|
|
|
|
Key2_X &= 0x0000007FFFFFFFFFULL;
|
|
|
|
|
Key2_Y &= 0x0000007FFFFFFFFFULL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
bool Init()
|
|
|
|
|
{
|
|
|
|
|
if (!NDSCart_SRAM::Init()) return false;
|
|
|
|
|
|
2017-03-20 10:39:42 -06:00
|
|
|
|
CartROM = NULL;
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void DeInit()
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2017-03-20 10:39:42 -06:00
|
|
|
|
if (CartROM) delete[] CartROM;
|
|
|
|
|
|
2017-02-07 14:23:46 -07:00
|
|
|
|
NDSCart_SRAM::DeInit();
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void Reset()
|
|
|
|
|
{
|
|
|
|
|
SPICnt = 0;
|
|
|
|
|
ROMCnt = 0;
|
|
|
|
|
|
|
|
|
|
memset(ROMCommand, 0, 8);
|
|
|
|
|
ROMDataOut = 0;
|
|
|
|
|
|
|
|
|
|
Key2_X = 0;
|
|
|
|
|
Key2_Y = 0;
|
|
|
|
|
|
|
|
|
|
memset(DataOut, 0, 0x4000);
|
|
|
|
|
DataOutPos = 0;
|
|
|
|
|
DataOutLen = 0;
|
|
|
|
|
|
|
|
|
|
CartInserted = false;
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (CartROM) delete[] CartROM;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
CartROM = NULL;
|
|
|
|
|
CartROMSize = 0;
|
|
|
|
|
CartID = 0;
|
2017-01-22 18:26:05 -07:00
|
|
|
|
CartIsHomebrew = false;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
CmdEncMode = 0;
|
|
|
|
|
DataEncMode = 0;
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
|
|
|
|
NDSCart_SRAM::Reset();
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-03-19 12:07:39 -06:00
|
|
|
|
bool LoadROM(const char* path, bool direct)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
// TODO: streaming mode? for really big ROMs or systems with limited RAM
|
|
|
|
|
// for now we're lazy
|
|
|
|
|
|
2017-03-20 10:39:42 -06:00
|
|
|
|
if (CartROM) delete[] CartROM;
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
FILE* f = fopen(path, "rb");
|
2017-02-07 15:31:21 -07:00
|
|
|
|
if (!f)
|
|
|
|
|
{
|
|
|
|
|
printf("Failed to open ROM file %s\n", path);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
fseek(f, 0, SEEK_END);
|
|
|
|
|
u32 len = (u32)ftell(f);
|
|
|
|
|
|
|
|
|
|
CartROMSize = 0x200;
|
|
|
|
|
while (CartROMSize < len)
|
|
|
|
|
CartROMSize <<= 1;
|
|
|
|
|
|
|
|
|
|
u32 gamecode;
|
|
|
|
|
fseek(f, 0x0C, SEEK_SET);
|
|
|
|
|
fread(&gamecode, 4, 1, f);
|
|
|
|
|
|
|
|
|
|
CartROM = new u8[CartROMSize];
|
|
|
|
|
memset(CartROM, 0, CartROMSize);
|
|
|
|
|
fseek(f, 0, SEEK_SET);
|
|
|
|
|
fread(CartROM, 1, len, f);
|
|
|
|
|
|
|
|
|
|
fclose(f);
|
|
|
|
|
//CartROM = f;
|
|
|
|
|
|
2017-03-19 12:07:39 -06:00
|
|
|
|
if (direct)
|
|
|
|
|
{
|
|
|
|
|
NDS::SetupDirectBoot();
|
|
|
|
|
CmdEncMode = 2;
|
|
|
|
|
}
|
2017-02-01 13:35:00 -07:00
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
CartInserted = true;
|
|
|
|
|
|
|
|
|
|
// generate a ROM ID
|
|
|
|
|
// note: most games don't check the actual value
|
|
|
|
|
// it just has to stay the same throughout gameplay
|
|
|
|
|
CartID = 0x00001FC2;
|
|
|
|
|
|
2017-01-22 18:26:05 -07:00
|
|
|
|
u32 arm9base = *(u32*)&CartROM[0x20];
|
|
|
|
|
if (arm9base < 0x8000)
|
|
|
|
|
{
|
|
|
|
|
if (arm9base >= 0x4000)
|
|
|
|
|
{
|
|
|
|
|
// reencrypt secure area if needed
|
2017-03-19 12:07:39 -06:00
|
|
|
|
if (*(u32*)&CartROM[arm9base] == 0xE7FFDEFF && *(u32*)&CartROM[arm9base+0x10] != 0xE7FFDEFF)
|
2017-01-22 18:26:05 -07:00
|
|
|
|
{
|
|
|
|
|
printf("Re-encrypting cart secure area\n");
|
|
|
|
|
|
|
|
|
|
strncpy((char*)&CartROM[arm9base], "encryObj", 8);
|
|
|
|
|
|
|
|
|
|
Key1_InitKeycode(gamecode, 3, 2);
|
|
|
|
|
for (u32 i = 0; i < 0x800; i += 8)
|
|
|
|
|
Key1_Encrypt((u32*)&CartROM[arm9base + i]);
|
|
|
|
|
|
|
|
|
|
Key1_InitKeycode(gamecode, 2, 2);
|
|
|
|
|
Key1_Encrypt((u32*)&CartROM[arm9base]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
CartIsHomebrew = true;
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
// encryption
|
|
|
|
|
Key1_InitKeycode(gamecode, 2, 2);
|
2017-02-03 08:57:31 -07:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// save
|
|
|
|
|
char savepath[256];
|
|
|
|
|
strncpy(savepath, path, 255);
|
|
|
|
|
savepath[255] = '\0';
|
|
|
|
|
strncpy(savepath + strlen(path) - 3, "sav", 3);
|
|
|
|
|
printf("Save file: %s\n", savepath);
|
|
|
|
|
NDSCart_SRAM::LoadSave(savepath);
|
2017-02-07 15:31:21 -07:00
|
|
|
|
|
|
|
|
|
return true;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ReadROM(u32 addr, u32 len, u32 offset)
|
|
|
|
|
{
|
|
|
|
|
if (!CartInserted) return;
|
|
|
|
|
|
|
|
|
|
if (addr >= CartROMSize) return;
|
|
|
|
|
if ((addr+len) > CartROMSize)
|
|
|
|
|
len = CartROMSize - addr;
|
|
|
|
|
|
|
|
|
|
memcpy(DataOut+offset, CartROM+addr, len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ReadROM_B7(u32 addr, u32 len, u32 offset)
|
|
|
|
|
{
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (!CartInserted) return;
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
addr &= (CartROMSize-1);
|
2017-01-22 18:26:05 -07:00
|
|
|
|
if (!CartIsHomebrew)
|
|
|
|
|
{
|
|
|
|
|
if (addr < 0x8000)
|
|
|
|
|
addr = 0x8000 + (addr & 0x1FF);
|
|
|
|
|
}
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
memcpy(DataOut+offset, CartROM+addr, len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
void ROMEndTransfer(u32 param)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
ROMCnt &= ~(1<<31);
|
|
|
|
|
|
|
|
|
|
if (SPICnt & (1<<14))
|
2017-03-02 16:48:26 -07:00
|
|
|
|
NDS::SetIRQ((NDS::ExMemCnt[0]>>11)&0x1, NDS::IRQ_CartSendDone);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ROMPrepareData(u32 param)
|
|
|
|
|
{
|
|
|
|
|
if (DataOutPos >= DataOutLen)
|
|
|
|
|
ROMDataOut = 0;
|
|
|
|
|
else
|
|
|
|
|
ROMDataOut = *(u32*)&DataOut[DataOutPos];
|
|
|
|
|
|
|
|
|
|
DataOutPos += 4;
|
|
|
|
|
|
|
|
|
|
ROMCnt |= (1<<23);
|
2017-04-11 12:21:31 -06:00
|
|
|
|
NDS::CheckDMAs(0, 0x05);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
NDS::CheckDMAs(1, 0x12);
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
void WriteROMCnt(u32 val)
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2017-04-11 12:21:31 -06:00
|
|
|
|
ROMCnt = (val & 0xFF7F7FFF) | (ROMCnt & 0x00800000);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
if (!(SPICnt & (1<<15))) return;
|
|
|
|
|
|
|
|
|
|
if (val & (1<<15))
|
|
|
|
|
{
|
|
|
|
|
u32 snum = (NDS::ExMemCnt[0]>>8)&0x8;
|
|
|
|
|
u64 seed0 = *(u32*)&NDS::ROMSeed0[snum] | ((u64)NDS::ROMSeed0[snum+4] << 32);
|
|
|
|
|
u64 seed1 = *(u32*)&NDS::ROMSeed1[snum] | ((u64)NDS::ROMSeed1[snum+4] << 32);
|
|
|
|
|
|
|
|
|
|
Key2_X = 0;
|
|
|
|
|
Key2_Y = 0;
|
|
|
|
|
for (u32 i = 0; i < 39; i++)
|
|
|
|
|
{
|
|
|
|
|
if (seed0 & (1ULL << i)) Key2_X |= (1ULL << (38-i));
|
|
|
|
|
if (seed1 & (1ULL << i)) Key2_Y |= (1ULL << (38-i));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
printf("seed0: %02X%08X\n", (u32)(seed0>>32), (u32)seed0);
|
|
|
|
|
printf("seed1: %02X%08X\n", (u32)(seed1>>32), (u32)seed1);
|
|
|
|
|
printf("key2 X: %02X%08X\n", (u32)(Key2_X>>32), (u32)Key2_X);
|
|
|
|
|
printf("key2 Y: %02X%08X\n", (u32)(Key2_Y>>32), (u32)Key2_Y);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (!(ROMCnt & (1<<31))) return;
|
|
|
|
|
|
|
|
|
|
u32 datasize = (ROMCnt >> 24) & 0x7;
|
|
|
|
|
if (datasize == 7)
|
|
|
|
|
datasize = 4;
|
|
|
|
|
else if (datasize > 0)
|
|
|
|
|
datasize = 0x100 << datasize;
|
|
|
|
|
|
|
|
|
|
DataOutPos = 0;
|
|
|
|
|
DataOutLen = datasize;
|
|
|
|
|
|
|
|
|
|
// handle KEY1 encryption as needed.
|
|
|
|
|
// KEY2 encryption is implemented in hardware and doesn't need to be handled.
|
|
|
|
|
u8 cmd[8];
|
|
|
|
|
if (CmdEncMode == 1)
|
|
|
|
|
{
|
|
|
|
|
*(u32*)&cmd[0] = ByteSwap(*(u32*)&ROMCommand[4]);
|
|
|
|
|
*(u32*)&cmd[4] = ByteSwap(*(u32*)&ROMCommand[0]);
|
|
|
|
|
Key1_Decrypt((u32*)cmd);
|
|
|
|
|
u32 tmp = ByteSwap(*(u32*)&cmd[4]);
|
|
|
|
|
*(u32*)&cmd[4] = ByteSwap(*(u32*)&cmd[0]);
|
|
|
|
|
*(u32*)&cmd[0] = tmp;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
*(u32*)&cmd[0] = *(u32*)&ROMCommand[0];
|
|
|
|
|
*(u32*)&cmd[4] = *(u32*)&ROMCommand[4];
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 18:26:05 -07:00
|
|
|
|
/*printf("ROM COMMAND %04X %08X %02X%02X%02X%02X%02X%02X%02X%02X SIZE %04X\n",
|
2017-01-22 12:34:59 -07:00
|
|
|
|
SPICnt, ROMCnt,
|
|
|
|
|
cmd[0], cmd[1], cmd[2], cmd[3],
|
|
|
|
|
cmd[4], cmd[5], cmd[6], cmd[7],
|
2017-01-22 18:26:05 -07:00
|
|
|
|
datasize);*/
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
|
|
|
|
switch (cmd[0])
|
|
|
|
|
{
|
|
|
|
|
case 0x9F:
|
|
|
|
|
memset(DataOut, 0xFF, DataOutLen);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x00:
|
|
|
|
|
memset(DataOut, 0, DataOutLen);
|
|
|
|
|
if (DataOutLen > 0x1000)
|
|
|
|
|
{
|
|
|
|
|
ReadROM(0, 0x1000, 0);
|
|
|
|
|
for (u32 pos = 0x1000; pos < DataOutLen; pos += 0x1000)
|
|
|
|
|
memcpy(DataOut+pos, DataOut, 0x1000);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ReadROM(0, DataOutLen, 0);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x90:
|
|
|
|
|
case 0xB8:
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = CartID;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x3C:
|
2017-03-29 10:59:20 -06:00
|
|
|
|
if (CartInserted) CmdEncMode = 1;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0xB7:
|
|
|
|
|
{
|
|
|
|
|
u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
|
|
|
|
|
memset(DataOut, 0, DataOutLen);
|
|
|
|
|
|
|
|
|
|
if (((addr + DataOutLen - 1) >> 12) != (addr >> 12))
|
|
|
|
|
{
|
|
|
|
|
u32 len1 = 0x1000 - (addr & 0xFFF);
|
|
|
|
|
ReadROM_B7(addr, len1, 0);
|
|
|
|
|
ReadROM_B7(addr+len1, DataOutLen-len1, len1);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ReadROM_B7(addr, DataOutLen, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
switch (cmd[0] & 0xF0)
|
|
|
|
|
{
|
|
|
|
|
case 0x40:
|
|
|
|
|
DataEncMode = 2;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 0x10:
|
|
|
|
|
for (u32 pos = 0; pos < DataOutLen; pos += 4)
|
|
|
|
|
*(u32*)&DataOut[pos] = CartID;
|
|
|
|
|
break;
|
|
|
|
|
|
2017-01-22 18:26:05 -07:00
|
|
|
|
case 0x20:
|
|
|
|
|
{
|
|
|
|
|
u32 addr = (cmd[2] & 0xF0) << 8;
|
|
|
|
|
ReadROM(addr, 0x1000, 0);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
case 0xA0:
|
|
|
|
|
CmdEncMode = 2;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
ROMCnt &= ~(1<<23);
|
|
|
|
|
|
|
|
|
|
// ROM transfer timings
|
|
|
|
|
// the bus is parallel with 8 bits
|
|
|
|
|
// thus a command would take 8 cycles to be transferred
|
|
|
|
|
// and it would take 4 cycles to receive a word of data
|
2017-01-22 12:34:59 -07:00
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
if (datasize == 0)
|
2017-04-11 12:21:31 -06:00
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, false, xfercycle*8, ROMEndTransfer, 0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
else
|
2017-04-11 12:21:31 -06:00
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*(8+4), ROMPrepareData, 0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
u32 ReadROMData()
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
2017-04-11 12:21:31 -06:00
|
|
|
|
if (ROMCnt & (1<<23))
|
2017-01-22 12:34:59 -07:00
|
|
|
|
{
|
|
|
|
|
ROMCnt &= ~(1<<23);
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
if (DataOutPos < DataOutLen)
|
|
|
|
|
{
|
|
|
|
|
u32 xfercycle = (ROMCnt & (1<<27)) ? 8 : 5;
|
|
|
|
|
NDS::ScheduleEvent(NDS::Event_ROMTransfer, true, xfercycle*4, ROMPrepareData, 0);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
ROMEndTransfer(0);
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-04-11 12:21:31 -06:00
|
|
|
|
return ROMDataOut;
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|
|
|
|
|
|
2017-01-31 09:34:17 -07:00
|
|
|
|
|
|
|
|
|
void WriteSPICnt(u16 val)
|
|
|
|
|
{
|
|
|
|
|
SPICnt = (SPICnt & 0x0080) | (val & 0xE043);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
u8 ReadSPIData()
|
|
|
|
|
{
|
|
|
|
|
if (!(SPICnt & (1<<15))) return 0;
|
|
|
|
|
if (!(SPICnt & (1<<13))) return 0;
|
|
|
|
|
|
|
|
|
|
return NDSCart_SRAM::Read();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void WriteSPIData(u8 val)
|
|
|
|
|
{
|
|
|
|
|
if (!(SPICnt & (1<<15))) return;
|
|
|
|
|
if (!(SPICnt & (1<<13))) return;
|
|
|
|
|
|
|
|
|
|
// TODO: take delays into account
|
|
|
|
|
|
|
|
|
|
NDSCart_SRAM::Write(val, SPICnt&(1<<6));
|
|
|
|
|
}
|
|
|
|
|
|
2017-01-22 12:34:59 -07:00
|
|
|
|
}
|